Re: Fast channel switching

On Mon, Feb 22, 2010 at 10:19 PM, IVAN KORSHUN <[email protected]> wrote:

> void ar5212SetChannel5112work2192(UINT32 freq)
> {
> /* Step 5 MHz */
>           UINT32       ii,channelSelect;
> volatile   UINT32 *hard_reg;
>
>        channelSelect = ((freq - 672) * 2 - 3040)/10;
>            channelSelect = (channelSelect << 2) & 0xff;
>            channelSelect = ath_hal_reverseBits(channelSelect, 8);
>
>
>        channelSelect = (channelSelect << 4) | 0x1005;
>
>        hard_reg = (void*)0xB8510024; *hard_reg = 0x0;
>        sysUDelayFlash (0x3E8);
>        hard_reg = (void*)0xb851981c; *hard_reg = 0x0;
>        sysUDelayFlash (0xA);
>        hard_reg = (void*)0xb851989C; *hard_reg = (channelSelect & 0xff);
>
>        channelSelect = (channelSelect >> 8) & 0x7f;
>        hard_reg = (void*)0xb85198D8; *hard_reg = channelSelect;
>        sysUDelayFlash (0xA);
>        hard_reg = (void*)0xb851981c; *hard_reg = 0x1;
>        sysUDelayFlash (0x64);
>        hard_reg = (void*)0xb8519860;
>        *hard_reg = *hard_reg |0x2;
>        channelSelect = 0x2;
>        for (ii=0; (ii< 0x3FFFE) && channelSelect ;ii++)channelSelect =
> *hard_reg & 0x2;
>
>        hard_reg = (void*)0xB8510024; *hard_reg = 0x1;
>
> }
>

Hi Ivan

Do you intend to suggest that I can call this function directly for
switching the frequency?? If so could you please explain as to what the
function does. You are setting the values for the variable, hard_reg and
channelSelect, but dont you need to set these values in the register so that
the hardware actually changes the channel?

 Also what is the definition for the function, sysUDelayFlash () since it is
not available in the madwifi code.

Thanks
Vishal

>
> -----Original Message-----
> From: Vishal Sevani <[email protected]>
> To: [email protected]
> Date: Mon, 22 Feb 2010 14:10:04 +0530
> Subject: Re: [Madwifi-users] Fast channel switching
>
> > On Sat, Feb 20, 2010 at 5:00 AM, Pavel Roskin <[email protected]> wrote:
> >
> > > On Fri, 2010-02-19 at 15:17 +0530, Vishal Sevani wrote:
> > >
> > > >         > I did apply the following patch
> > > >         > https://madwifi-project.org/ticket/2322 , but to no avail.
> > > >         Could you
> > > >         > point out as to what the problem could be?? If you need me
> > > >         to provide
> > > >         > any other debug information please do let me know.
> > > >
> > > >
> > > >         I'll appreciate if you post your results to the ticket.  So
> > > >         far there
> > > >         have been no test results for that patch at all.
> > > >
> > > > Yeah I have posted my experience in the following ticket.
> > > > https://madwifi-project.org/ticket/2359
> > >
> > > I actually I meant that you would report a negative result with the
> > > patch in #2322.  But it looks like the problems are different.
> > >
> > > Yeah it seems more of a hardware issue with AR71xx borad, (or issue
> with
> > Openwrt) as pointed out by [email protected] in his comment following
> yours
> > in the ticket #2359. If Iam correct, it is happening because the value in
> > reg AR_ISR corresponding to flag AR_ISR_HIUERR is being set, which is for
> > unexpected bus error. As mentioned in the following post
> > http://n2.nabble.com/fatal-interrupt-td3225930.html, it is beacuse the
> > following bit, AR_ISR_S2_MCABT  (for master cycle abort) is being set.
> >
> > Iam clueless as to what could be causing this master cycle abort problem
> and
> > how should I go about debugging it. Could you please provide any pointers
> as
> > to how I can rectify this problem.
> >
> >
> > > > Yesterday again I tried with latest release of Openwrt Kamikaze  ie.
> > > > v8.09.2, but still I get the same problem. But the madwifi code works
> > > > properly on IBM latop running Ubuntu with Linux kernel 2.6.24-23. So
> I
> > > > guess it is the issue with Openwrt or the hardware ie. AR71xx boards.
> > > > Has the latest code been tested on Openwrt and Ar71xx boards??
> > >
> > > I'm not aware of it.
> > >
> > > --
> > > Regards,
> > > Pavel Roskin
> > >
> >
> >
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>
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proactively, and fine-tune applications for parallel performance.
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