Re: MadWifi driver fails to recognize Ubiquity card

On Wed, 2010-07-14 at 17:52 -0400, Aditya Bhave wrote: 
> Even with the trunk version, the same problem occurs. No wifi0 appears

I guess lshw is wrong and you actually have an AR9220 card.  Please keep
in mind that the output of "lspci -nn" is more useful.

AR9220 is not currently supported, but I made a patch for it.  I'm not
ready to commit it now because it seems somewhat inelegant and most
importantly because I didn't test it on any PCI Express devices yet.

Please test and report results.

Add AR9220 support

From: Pavel Roskin <[email protected]>


---
 ath/if_ath_pci.c               |    4 +---
 ath_hal/ah.c                   |   19 +++++++++++++++++++
 ath_hal/ah_eeprom.h            |    1 +
 ath_hal/ah_eeprom_v14.c        |    3 +++
 ath_hal/ah_internal.h          |    3 +++
 ath_hal/ar5416/ar5416.h        |    1 +
 ath_hal/ar5416/ar5416_reset.c  |    5 ++---
 ath_hal/ar5416/ar9280_attach.c |   18 ++++++++++++++----
 8 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/ath/if_ath_pci.c b/ath/if_ath_pci.c
index 71e0fe7..ff41070 100644
--- a/ath/if_ath_pci.c
+++ b/ath/if_ath_pci.c
@@ -114,9 +114,7 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = {
 	{ 0x168c, 0x0023, PCI_ANY_ID, PCI_ANY_ID },
 	{ 0x168c, 0x0024, PCI_ANY_ID, PCI_ANY_ID },
 	{ 0x168c, 0x0027, PCI_ANY_ID, PCI_ANY_ID },
-#if 0 /* PCI based AR9280 doesn't work yet */
-	{ 0x168c, 0x0029, PCI_ANY_ID, PCI_ANY_ID }, /* AR9280 PCI */
-#endif
+	{ 0x168c, 0x0029, PCI_ANY_ID, PCI_ANY_ID }, /* AR9220 PCI */
 	{ 0x168c, 0x002a, PCI_ANY_ID, PCI_ANY_ID }, /* AR9280 PCI Express */
 	{ 0x168c, 0x9013, PCI_ANY_ID, PCI_ANY_ID }, /* sonicwall */
 	{ 0 }
diff --git a/ath_hal/ah.c b/ath_hal/ah.c
index 668ace7..2cecf93 100644
--- a/ath_hal/ah.c
+++ b/ath_hal/ah.c
@@ -862,6 +862,25 @@ ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
 	return regWr;
 }
 
+int
+ath_hal_ini_write_masked(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+	int col, int regWr, uint32_t maskreg, uint32_t mask)
+{
+	int r;
+	uint32_t reg, val;
+
+	for (r = 0; r < ia->rows; r++) {
+		reg = HAL_INI_VAL(ia, r, 0);
+		val = HAL_INI_VAL(ia, r, col);
+		if (reg == maskreg)
+			val &= ~mask;
+
+		OS_REG_WRITE(ah, reg, val);
+		DMA_YIELD(regWr);
+	}
+	return regWr;
+}
+
 void
 ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, int col)
 {
diff --git a/ath_hal/ah_eeprom.h b/ath_hal/ah_eeprom.h
index 0adfcd1..f308912 100644
--- a/ath_hal/ah_eeprom.h
+++ b/ath_hal/ah_eeprom.h
@@ -99,6 +99,7 @@ enum {
 	AR_EEP_ANTGAINMAX_5,	/* int8_t* */
 	AR_EEP_ANTGAINMAX_2,	/* int8_t* */
 	AR_EEP_WRITEPROTECT,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_PWDCLKIND,	/* int8_t* */
 };
 
 typedef struct {
diff --git a/ath_hal/ah_eeprom_v14.c b/ath_hal/ah_eeprom_v14.c
index 8793d3b..412cf21 100644
--- a/ath_hal/ah_eeprom_v14.c
+++ b/ath_hal/ah_eeprom_v14.c
@@ -120,6 +120,9 @@ v14EepromGet(struct ath_hal *ah, int param, void *val)
 	case AR_EEP_ANTGAINMAX_5:
 		*(int8_t *) val = ee->ee_antennaGainMax[0];
 		return HAL_OK;
+	case AR_EEP_PWDCLKIND:
+		*(int8_t *) val = pBase->pwdclkind;
+		return HAL_OK;
         default:
 		HALASSERT(0);
 		return HAL_EINVAL;
diff --git a/ath_hal/ah_internal.h b/ath_hal/ah_internal.h
index eb452fa..1d8cfd8 100644
--- a/ath_hal/ah_internal.h
+++ b/ath_hal/ah_internal.h
@@ -796,6 +796,9 @@ typedef struct {
 
 extern	int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
 		int col, int regWr);
+extern	int ath_hal_ini_write_masked(struct ath_hal *ah,
+		const HAL_INI_ARRAY *ia, int col, int regWr, uint32_t maskreg,
+		uint32_t mask);
 extern	void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
 		int col);
 extern	int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
diff --git a/ath_hal/ar5416/ar5416.h b/ath_hal/ar5416/ar5416.h
index d92641a..2c825d4 100644
--- a/ath_hal/ar5416/ar5416.h
+++ b/ath_hal/ar5416/ar5416.h
@@ -77,6 +77,7 @@ struct ath_hal_5416 {
 	uint32_t	ah_extBusy;
 	uint32_t	ah_rx_chainmask;
 	uint32_t	ah_tx_chainmask;
+	uint32_t	ah_pwdclkmask;
 
 	struct ar5416PerCal ah_cal;		/* periodic calibration state */
 };
diff --git a/ath_hal/ar5416/ar5416_reset.c b/ath_hal/ar5416/ar5416_reset.c
index 43013f4..4984c20 100644
--- a/ath_hal/ar5416/ar5416_reset.c
+++ b/ath_hal/ar5416/ar5416_reset.c
@@ -270,10 +270,9 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
 	    regWrites);
 	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
 
-	/* XXX Merlin ini fixups */
 	/* XXX Merlin 100us delay for shift registers */
-	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex,
-	    regWrites);
+	regWrites = ath_hal_ini_write_masked(ah, &ahp->ah_ini_modes, modesIndex,
+	    regWrites, AR_AN_TOP2, AH5416(ah)->ah_pwdclkmask);
 #ifdef AH_SUPPORT_AR9280
 	if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
 		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
diff --git a/ath_hal/ar5416/ar9280_attach.c b/ath_hal/ar5416/ar9280_attach.c
index 5281add..b684aa5 100644
--- a/ath_hal/ar5416/ar9280_attach.c
+++ b/ath_hal/ar5416/ar9280_attach.c
@@ -87,6 +87,7 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
 	uint32_t val;
 	HAL_STATUS ecode;
 	HAL_BOOL rfStatus;
+	uint8_t pwdclkind;
 
 	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
 	    __func__, sc, (void*) st, (void*) sh);
@@ -166,6 +167,11 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
 	if (ecode != HAL_OK)
 		goto bad;
 
+	if (!AH_PRIVATE(ah)->ah_ispcie &&
+	    (ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND,
+		&pwdclkind) == HAL_OK) && !pwdclkind)
+		AH5416(ah)->ah_pwdclkmask = AR_AN_TOP2_PWDCLKIND;
+
 	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
 		ecode = HAL_EIO;
@@ -334,16 +340,20 @@ ar9280WriteIni(struct ath_hal *ah, const HAL_CHANNEL *chan)
 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
 	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
 
-	/* XXX Merlin ini fixups */
 	/* XXX Merlin 100us delay for shift registers */
-	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
-	    modesIndex, regWrites);
 	if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
 		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
 		    modesIndex, regWrites);
 		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
 		    modesIndex, regWrites);
-	}
+		regWrites = ath_hal_ini_write_masked(ah,
+		    &AH5212(ah)->ah_ini_modes, modesIndex, regWrites,
+		    AR_AN_TOP2, AH5416(ah)->ah_pwdclkmask);
+
+	} else
+		regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
+		    modesIndex, regWrites);
+
 	/* XXX Merlin 100us delay for shift registers */
 	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
 	    1, regWrites);


-- 
Regards,
Pavel Roskin


------------------------------------------------------------------------------
This SF.net email is sponsored by Sprint
What will you do first with EVO, the first 4G phone?
Visit sprint.com/first -- http://p.sf.net/sfu/sprint-com-first