Re: [PATCH 04/30] mtd: spi-nor: winbond: Make the RDCR fixup Winbond wide

On 06/07/2026 at 16:11:31 +02, "Michael Walle" <[email protected]> wrote:

> On Fri May 29, 2026 at 5:22 PM CEST, Miquel Raynal wrote:
>> The top level paragraph of the QER field in the JESD216B mentions:
>>
>> "In this standard, [...]  Status register 2 refers to the byte read
>> using instruction 35h. Status register 2 is the second byte transferred
>> in a Write Status (01h) command. [...]"
>>
>> Value 100b, named in Linux BFPT_DWORD15_QER_SR2_BIT1_NO_RD, does not
>> mention anything about reads and only brings details about writes.
>>
>> This has been interpreted in the spi-nor core by the absence of read
>> capability, but there is no explicit reason for that, except that there
>> were probably some very old chips which didn't support command 35h.
>
> I agree. But making it a vendor default we always have to have an
> entry. So if this is really for all winbond chips, we shall do a
> catch all entry (like in macronix.c).

Good catch, I didn't think about that. Added.

[...]

>> +	if (nor->info->id->bytes[0] =3D=3D 0xef &&
>> +	    nor->info->id->bytes[1] > 0x30)
>> +		nor->flags &=3D ~SNOR_F_NO_READ_CR;
>
> This is somewhat hard to read and the byte[0] is redundant here.
> Maybe you can come up with some macro magic sugar :)

I dropped the first condition in the if which indeed is
redundant. However I don't know how to make the remainder more
explanatory, there is already a big comment telling why we do it.

Thanks!
Miqu=C3=A8l