Re: RX overrun with 3COM 3c982

Donald Becker wrote:

>On Wed, 13 Nov 2002, Claude Pignol wrote:
>
>  
>
>>>The only source for FIFO errors with this speicific chip is the errors
>>>reported in Window 6 offset 5.
>>>These errors can occur either because
>>>  The chip ran out of PCI bandwidth
>>>  The driver ran out of receive buffers, causing the PCI Rx transfers
>>>  (the "upload engine") to stall.
>>>
>>>Are you running another high-bandwidth PCI device on the system?  Video
>>>cards are the usual offenders.
>>>      
>>>
>...
>  
>
>>00:08.0 RAID bus controller: 3ware Inc 3ware ATA-RAID (rev 12)
>>    
>>
>
>Hmmm, this might be doing long PCI bursts, not leaving enough for the
>Ethernet.  If that's the case, the solution is to:
>   Change the Min-grant / Max-Latency PCI settings
>   Set the PCI bursts to much longer values, although the '982 has
>     reasonable defaults.  The registers to change are the
>     UpBurstThreshold at offset 0x3e and
>     UpPriorityThreshold, offset 0x3c, default 4*32 = 128 bytes.
>
>You can read the maximum burst that actually happened at offset 0x7a
>using vortex-diag.  I wouldn't change the UpPriorityThreshold except for
>debugging -- 128 bytes is already a too-low value for whole-frame Rx bursts.
>
>
>  
>
Well, I am little bit lost:
Is offset 7a (windows 7 and 10th byte): it's always 0??
I don't know how to change the value of 0x3c
and 0x3e. but before trying to change them it's a good thing to locate 
them.

Window 3: 0000 0180 05ea 0020 000a 0800 0800 6000
0x3c contains 08 and 0x3e 60
Is it correct?

Thanks
CP






>  
>

-- 
------------------------------------------------------------------------
Claude Pignol SeismicCity, Inc. <http://www.seismiccity.com>
2900 Wilcrest Dr. Suite 370 Houston TX 77042
Phone:832 251 1471 Mob:281 703 2933 Fax:832 251 0586



_______________________________________________
vortex mailing list
[email protected]
http://www.scyld.com/mailman/listinfo/vortex