Re: atyfb: brokenness on PowerMac 5500 and Beige G3

On Fri, Oct 28, 2005 at 10:18:36PM +0200, Geert Uytterhoeven wrote:
> On Fri, 28 Oct 2005, coutal coutal wrote:
> > i am using the atyfb driver on my powermac 5500 (ati rage II 215GT). after
> > upgrading the kernel, three vertical bands of visible distortion appeared in
> > my console. they are not videomode-tied (tried almost all my card supports)
> > and thus i suspect some breakage in the driver.
> 
> Which kernel version worked fine? Which one caused the regression?
> 
> > can anyone please have a look at it?
> > moreover, what could cause such an effect? would it be memory clock or pll
> > programming? please enlighten me a bit, i am curious.
> 
> This looks more like a problem with the display FIFO programming (DSP_*
> registers): some RAGE chips have 24 entries in the display FIFO, others have
> 32.

One thing that sticks out is dsp_loop_latency. This patch changes the 
calculation to be more like the old way. It's still a bit different since 
the new code takes more memory types into consideration. Completely 
untested on any hardware...

--- mach64_ct.c.orig	2005-10-29 14:05:40.000000000 +0300
+++ mach64_ct.c	2005-10-29 14:10:37.000000000 +0300
@@ -425,8 +425,10 @@
 
 	if (M64_HAS(FIFO_32)) {
 		pll->ct.fifo_size = 32;
+		pll->ct.dsp_loop_latency = 2;
 	} else {
 		pll->ct.fifo_size = 24;
+		pll->ct.dsp_loop_latency = 0;
 		pll->ct.xclkpagefaultdelay += 2;
 		pll->ct.xclkmaxrasdelay += 3;
 	}
@@ -434,35 +436,35 @@
 	switch (par->ram_type) {
 	case DRAM:
 		if (info->fix.smem_len<=ONE_MB) {
-			pll->ct.dsp_loop_latency = 10;
+			pll->ct.dsp_loop_latency += 8;
 		} else {
-			pll->ct.dsp_loop_latency = 8;
+			pll->ct.dsp_loop_latency += 6;
 			pll->ct.xclkpagefaultdelay += 2;
 		}
 		break;
 	case EDO:
 	case PSEUDO_EDO:
 		if (info->fix.smem_len<=ONE_MB) {
-			pll->ct.dsp_loop_latency = 9;
+			pll->ct.dsp_loop_latency += 7;
 		} else {
-			pll->ct.dsp_loop_latency = 8;
+			pll->ct.dsp_loop_latency += 6;
 			pll->ct.xclkpagefaultdelay += 1;
 		}
 		break;
 	case SDRAM:
 		if (info->fix.smem_len<=ONE_MB) {
-			pll->ct.dsp_loop_latency = 11;
+			pll->ct.dsp_loop_latency += 9;
 		} else {
-			pll->ct.dsp_loop_latency = 10;
+			pll->ct.dsp_loop_latency += 8;
 			pll->ct.xclkpagefaultdelay += 1;
 		}
 		break;
 	case SGRAM:
-		pll->ct.dsp_loop_latency = 8;
+		pll->ct.dsp_loop_latency += 6;
 		pll->ct.xclkpagefaultdelay += 3;
 		break;
 	default:
-		pll->ct.dsp_loop_latency = 11;
+		pll->ct.dsp_loop_latency += 9;
 		pll->ct.xclkpagefaultdelay += 3;
 		break;
 	}

-- 
Ville Syrjälä
[email protected]
http://www.sci.fi/~syrjala/


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