Re: atyfb: brokenness on PowerMac 5500 and Beige G3

On Mon, Oct 31, 2005 at 09:07:32AM +0200, Gil Bahat wrote:
> Hello,
> 
>  
> 
> I suspect I have found the reason for the breakage I reported earlier in the
> driver - but I'd be very happy if someone was confirming that my attempt
> wouldn't mess up my hardware before I set off to test it.
> 
>  
> 
> This addition:
> 
>  
> 
> +   /* according to ATI, we should use clock 3 for acelerated mode */
> +   par->clk_wr_offset = 3;
> 
>  
> 
> comes up right after a nice piece of code that actually tries to mask
> clk_wr_offset:
> 
>  
> 
> +   if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
> +      par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
> +   else
> +      par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
> 
>  
> 
> and so makes this code redundant with a static value that "seems" to come
> out of nowhere.

clk_wr_offset just decides which VCLK "preset slot" we use to store the 
VCLK settings. It won't make any real difference which one is used. It's 
just some standard to use the last slot. I guess the lower slots are 
typically used for storing VGA clock settings or something like that.

> Furthermore, looking at atyfb.h, this particular register has overloaded
> meaning (by its comment) so it may cause the unexpected results I'm seeing.

I think that just means that it's used with GX chips as an actual write
offset. With CT chips it's used as a clock id which is actaully the same
thing as the preset slot thin I said earlier. In other words it has 
nothing to do with your case.

Did you try the dsp_loop_latency patch I sent earlier?

-- 
Ville Syrjälä
[email protected]
http://www.sci.fi/~syrjala/


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