PXA frame buffer not enabled in 1 bit per pixel mode.

Hi All,

Please note that I am now a suscribed member so if a previous email of
the same subject does make it through the moderator, ignore it.

I have a question regarding the PXA framebuffer support.  I've emailed
the ARM linux list but to no avail.  We've configured uboot to talk to
the LCD connected to our board and the LCD works fine.

Setting up the pxafb for the kernel is proving somewhat more testing.
Kernel is 2.6.15.1 with no patches to the video drivers.

My current modprobe looks like this;
modprobe pxafb \
options=mode:320x240-1,mono,single,vsynclen:3,hsynclen:1,left:1, \
right:1,upper:1,lower:1,vsync:1,hsync:1,pixclockpol:0,4pix, \
pixclock:643023

This gives the same LCCRX register setup as uboot was configured for,
with just 2 differences.
LCCR0_PDD=1 in uboot, =0 from pxafb.
LCCR0_QDM=0 in uboot, =1 from pxafb.

I forced LCCR0_PDD on but with no effect.

I turned on some debugging and got the following;
pxa2xx-fb pxa2xx-fb: overriding resolution: 320x240
pxa2xx-fb pxa2xx-fb: overriding bit depth: 1
pxa2xx-fb pxa2xx-fb: override vsynclen: 3
pxa2xx-fb pxa2xx-fb: override hsynclen: 1
pxa2xx-fb pxa2xx-fb: override left: 1
pxa2xx-fb pxa2xx-fb: override right: 1
pxa2xx-fb pxa2xx-fb: override upper: 1
pxa2xx-fb pxa2xx-fb: override lower: 1
pxa2xx-fb pxa2xx-fb: override vsync: Active High
pxa2xx-fb pxa2xx-fb: override hsync: Active High
pxa2xx-fb pxa2xx-fb: override pixel clock polarity: falling edge
pxa2xx-fb pxa2xx-fb: override pixclock: 643023
pxa2xx-fb pxa2xx-fb: Upper and lower margins must be 0 in passive mode

*** Why is this so?  It worked with uboot with these settings!***

pxafb: palette_mem_size = 0x00000020
pxafb: set_par
pxafb: palette_mem_size = 0x00000008
pxafb: true_color = 0
pxafb: Configuring PXA LCD
var: xres=320 hslen=1 lm=1 rm=1
var: yres=240 vslen=3 um=1 bm=1
var: pixclock=643023 pcd=32
nlccr0 = 0x0030187a
nlccr1 = 0x0000013f
nlccr2 = 0x010108ef
nlccr3 = 0x00400020
pxafb: Enabling LCD controller
fdadr0 0xa7fd4fe8
fdadr1 0xa7fd4fc8
reg_lccr0 0x0030187a
reg_lccr1 0x0000013f
reg_lccr2 0x010108ef
reg_lccr3 0x00400020
FDADR0 0xa7fd4fe0
FDADR1 0xa7fd4fc0
LCCR0 0x0030187b
LCCR1 0x0000013f
LCCR2 0x010108ef
LCCR3 0x00400020
pxafb: LCD power on
pxafb: backlight on

However when I run pxaregs LCCR0 I find that the LCCR0_ENB is not set -
but the debug shows it was set by the driver.

So who's disabling the FB?

If I spec 320x240-8, the enable bit stays set and I get a screen full of
beautiful vertical lines about 4 pixels appart - not very useful.

Any ideas where I'm going wrong?

I did RTFM and googled too but still don't see what the problem is.

Regards,
James.



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