Re: PXA frame buffer not enabled in 1 bit per pixel mode.

On Sat, 2006-02-18 at 12:52 +1100, James Steward wrote:
> On Fri, 2006-02-17 at 17:31 +0800, Antonino A. Daplas wrote:
> > James Steward wrote:
> > > pxa2xx-fb pxa2xx-fb: Upper and lower margins must be 0 in passive mode
> > > 
> > > *** Why is this so?  It worked with uboot with these settings!***
> > 
> > These are just over-verbose messages...
> 
> Ok, I'll ignore then.
> 
> > > So who's disabling the FB?
> > 
> > Try unconditinally calling pxafb_schedule_work() in pxafb_activate_var().
> > Then reread the register.
> > 
> 
> Thanks Tony!  I'll give it a try first thing Monday morning.
> 
Sorry Tony but that didn't seem to do anything for me.
I've since added more debuggery...

pxafb: Configuring PXA LCD
var: xres=320 hslen=1 lm=1 rm=1
var: yres=240 vslen=3 um=1 bm=1
var: pixclock=643023 pcd=32
nlccr0 = 0x0030187a          <-- The enable bit[0] is not set.
nlccr1 = 0x0000013f
nlccr2 = 0x010108ef
nlccr3 = 0x00400020
fbi->dmadesc_fblow_cpu = 0xffc00fc8
fbi->dmadesc_fbhigh_cpu = 0xffc00fd8
fbi->dmadesc_palette_cpu = 0xffc00fe8
fbi->dmadesc_fblow_dma = 0xa73f0fc8
fbi->dmadesc_fbhigh_dma = 0xa73f0fd8
fbi->dmadesc_palette_dma = 0xa73f0fe8
fbi->dmadesc_fblow_cpu->fdadr = 0xa73f0fc8
fbi->dmadesc_fbhigh_cpu->fdadr = 0xa73f0fe8
fbi->dmadesc_palette_cpu->fdadr = 0xa73f0fd8
fbi->dmadesc_fblow_cpu->fsadr = 0xa73f3580
fbi->dmadesc_fbhigh_cpu->fsadr = 0xa73f1000
fbi->dmadesc_palette_cpu->fsadr = 0xa73f0ff8
fbi->dmadesc_fblow_cpu->ldcmd = 0x2580
fbi->dmadesc_fbhigh_cpu->ldcmd = 0x2580
fbi->dmadesc_palette_cpu->ldcmd = 0x4000008
pxafb: Enabling LCD controller
fdadr0 0xa73f0fe8
fdadr1 0xa73f0fc8
reg_lccr0 0x0030187a     <-- The enable bit[0] is still not set.
reg_lccr1 0x0000013f
reg_lccr2 0x010108ef
reg_lccr3 0x00400020
pxafb: End of enabling LCD controller
FDADR0 0x00000000
FDADR1 0xa73f0fc0
LCCR0 0x0030187b        <-- Code in the enable routine sets bit[0]
LCCR1 0x0000013f
LCCR2 0x010108ef
LCCR3 0x00400020
pxafb: LCD power on
pxafb: backlight on
End of set_ctrlr_state state 7->1   {old state -> new state}
FDADR0 0x00000000
FDADR1 0xa73f0fc0
LCCR0 0x0030187b  <-- bit[0] still set at the end of set_ctrlr_state
LCCR1 0x0000013f
LCCR2 0x010108ef
LCCR3 0x00400020
End of set_ctrlr_state state 1->1   {old state -> new state}
FDADR0 0xea000210
FDADR1 0xa73f0fc0
LCCR0 0x0030187a  <-- bit[0] for some reason now cleared!!
LCCR1 0x0000013f
LCCR2 0x010108ef
LCCR3 0x00400020

So set_ctrlr_state is called a second time and afterwards the enable bit
is cleared.

Any further thoughts?

Regards,
James.



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