[libata sata_sil] Don't presume PCI cache-line-size reg is > 0
Linux Kernel Mailing List <[email protected]> Tue, 29 Mar 2005 20:43:38 +0000
| Newsgroups | gmane.linux.kernel.commits.2-4 |
|---|---|
| Message-ID | <[email protected]> |
ChangeSet 1.1448.129.6, 2005/03/29 15:43:38-05:00, [email protected] [libata sata_sil] Don't presume PCI cache-line-size reg is > 0 Some BIOSen are known to screw up the PCI cache-line-size register, so add a paranoia check. sata_sil.c | 16 ++++++++++------ 1 files changed, 10 insertions(+), 6 deletions(-) diff -Nru a/drivers/scsi/sata_sil.c b/drivers/scsi/sata_sil.c --- a/drivers/scsi/sata_sil.c 2005-04-30 12:15:31 -07:00 +++ b/drivers/scsi/sata_sil.c 2005-04-30 12:15:31 -07:00 @@ -421,12 +421,16 @@ /* Initialize FIFO PCI bus arbitration */ cls = sil_get_device_cache_line(pdev); - cls >>= 3; - cls++; /* cls = (line_size/8)+1 */ - writeb(cls, mmio_base + SIL_FIFO_R0); - writeb(cls, mmio_base + SIL_FIFO_W0); - writeb(cls, mmio_base + SIL_FIFO_R1); - writeb(cls, mmio_base + SIL_FIFO_W2); + if (cls) { + cls >>= 3; + cls++; /* cls = (line_size/8)+1 */ + writeb(cls, mmio_base + SIL_FIFO_R0); + writeb(cls, mmio_base + SIL_FIFO_W0); + writeb(cls, mmio_base + SIL_FIFO_R1); + writeb(cls, mmio_base + SIL_FIFO_W2); + } else + printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n", + pci_name(pdev)); if (ent->driver_data == sil_3114) { irq_mask = SIL_MASK_4PORT;