[PATCH] : Workaround 5752 A0 chip ID
Linux Kernel Mailing List <[email protected]> Tue, 24 May 2005 12:43:08 +0000
| Newsgroups | gmane.linux.kernel.commits.2-4 |
|---|---|
| Message-ID | <[email protected]> |
ChangeSet 1.1541, 2005/05/24 09:43:08-03:00, [email protected] [PATCH] : Workaround 5752 A0 chip ID [TG3]: Workaround 5752 A0 chip ID The 5752 A0 chip ID is wrong in hardware. The simplest way to workaround it is to change it to the correct value in tp->pci_chip_rev_id. This way, it is easier to check for the ASIC_REV_5752 in the rest of the driver. Signed-off-by: Michael Chan <[email protected]> Signed-off-by: David S. Miller <[email protected]> tg3.c | 9 +++++++-- tg3.h | 6 +++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff -Nru a/drivers/net/tg3.c b/drivers/net/tg3.c --- a/drivers/net/tg3.c 2005-05-24 14:05:51 -07:00 +++ b/drivers/net/tg3.c 2005-05-24 14:05:51 -07:00 @@ -7917,6 +7917,12 @@ tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT); + /* Wrong chip ID in 5752 A0. This code can be removed later + * as A0 is not in production. + */ + if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) + tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; + /* Initialize misc host control in PCI block. */ tp->misc_host_ctrl |= (misc_ctrl_reg & MISC_HOST_CTRL_CHIPREV); @@ -7932,8 +7938,7 @@ tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A0 || - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A1) + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || diff -Nru a/drivers/net/tg3.h b/drivers/net/tg3.h --- a/drivers/net/tg3.h 2005-05-24 14:05:51 -07:00 +++ b/drivers/net/tg3.h 2005-05-24 14:05:51 -07:00 @@ -125,7 +125,8 @@ #define CHIPREV_ID_5750_A0 0x4000 #define CHIPREV_ID_5750_A1 0x4001 #define CHIPREV_ID_5750_A3 0x4003 -#define CHIPREV_ID_5752_A0 0x5000 +#define CHIPREV_ID_5752_A0_HW 0x5000 +#define CHIPREV_ID_5752_A0 0x6000 #define CHIPREV_ID_5752_A1 0x6001 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) #define ASIC_REV_5700 0x07 @@ -134,8 +135,7 @@ #define ASIC_REV_5704 0x02 #define ASIC_REV_5705 0x03 #define ASIC_REV_5750 0x04 -#define ASIC_REV_5752_A0 0x05 -#define ASIC_REV_5752_A1 0x06 +#define ASIC_REV_5752 0x06 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) #define CHIPREV_5700_AX 0x70 #define CHIPREV_5700_BX 0x71