clk: ingenic: Fix recalc_rate for clocks with fixed divider

Web:        https://git.kernel.org/torvalds/c/e6cfa64375d34a6c8c1861868a381013b2d3b921
Commit:     e6cfa64375d34a6c8c1861868a381013b2d3b921
Parent:     ee1f9df26972fd736e0b2f52ad19935046bbc189
Refname:    refs/heads/master
Author:     Paul Cercueil <[email protected]>
AuthorDate: Tue Jan 16 16:47:52 2018 +0100
Committer:  James Hogan <[email protected]>
CommitDate: Thu Jan 18 22:04:56 2018 +0000

    clk: ingenic: Fix recalc_rate for clocks with fixed divider
    
    Previously, the clocks with a fixed divider would report their rate
    as being the same as the one of their parent, independently of the
    divider in use. This commit fixes this behaviour.
    
    This went unnoticed as neither the jz4740 nor the jz4780 CGU code
    have clocks with fixed dividers yet.
    
    Signed-off-by: Paul Cercueil <[email protected]>
    Acked-by: Stephen Boyd <[email protected]>
    Cc: Ralf Baechle <[email protected]>
    Cc: Maarten ter Huurne <[email protected]>
    Cc: [email protected]
    Patchwork: https://patchwork.linux-mips.org/patch/18477/
    Signed-off-by: James Hogan <[email protected]>
---
 drivers/clk/ingenic/cgu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index ab393637f7b0..a2e73a6d60fd 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 		div *= clk_info->div.div;
 
 		rate /= div;
+	} else if (clk_info->type & CGU_CLK_FIXDIV) {
+		rate /= clk_info->fixdiv.div;
 	}
 
 	return rate;
--
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