iommu/vt-d: Add a check for 5-level paging support
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Web: https://git.kernel.org/torvalds/c/f1ac10c24efbbcba0f8dae37ee90d45847f5c5af Commit: f1ac10c24efbbcba0f8dae37ee90d45847f5c5af Parent: 59103caa6839592788e7ad58b35863aac034631a Refname: refs/heads/master Author: Sohil Mehta <[email protected]> AuthorDate: Wed Dec 20 11:59:26 2017 -0800 Committer: Joerg Roedel <[email protected]> CommitDate: Wed Jan 17 15:02:50 2018 +0100 iommu/vt-d: Add a check for 5-level paging support Add a check to verify IOMMU 5-level paging support. If the CPU supports supports 5-level paging but the IOMMU does not support it then disable SVM by not allocating PASID tables. Signed-off-by: Sohil Mehta <[email protected]> Signed-off-by: Joerg Roedel <[email protected]> --- drivers/iommu/intel-svm.c | 4 ++++ include/linux/intel-iommu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index e9a56ad09a76..b43dc1edcef0 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -45,6 +45,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) !cap_fl1gp_support(iommu->cap)) return -EINVAL; + if (cpu_feature_enabled(X86_FEATURE_LA57) && + !cap_5lp_support(iommu->cap)) + return -EINVAL; + /* Start at 2 because it's defined as 2^(1+PSS) */ iommu->pasid_max = 2 << ecap_pss(iommu->ecap); diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index a56bab114f39..8dad3dd26eae 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -83,6 +83,7 @@ /* * Decoding Capability Register */ +#define cap_5lp_support(c) (((c) >> 60) & 1) #define cap_pi_support(c) (((c) >> 59) & 1) #define cap_fl1gp_support(c) (((c) >> 56) & 1) #define cap_read_drain(c) (((c) >> 55) & 1) -- To unsubscribe from this list: send the line "unsubscribe git-commits-head" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html