KVM: VMX: introduce X2APIC_MSR macro

Web:        https://git.kernel.org/torvalds/c/d7231e75f73f424068ad205358bd8ba6a7a2e113
Commit:     d7231e75f73f424068ad205358bd8ba6a7a2e113
Parent:     c992384bde84fb2f0318bdb4f6c710605dd7a217
Refname:    refs/heads/master
Author:     Paolo Bonzini <[email protected]>
AuthorDate: Thu Dec 21 00:47:55 2017 +0100
Committer:  Radim Krčmář <[email protected]>
CommitDate: Tue Jan 16 16:52:52 2018 +0100

    KVM: VMX: introduce X2APIC_MSR macro
    
    Remove duplicate expression in nested_vmx_prepare_msr_bitmap, and make
    the register names clearer in hardware_setup.
    
    Suggested-by: Jim Mattson <[email protected]>
    Reviewed-by: Jim Mattson <[email protected]>
    Signed-off-by: Paolo Bonzini <[email protected]>
    [Resolved rebase conflict after removing Intel PT. - Radim]
    Signed-off-by: Radim Krčmář <[email protected]>
---
 arch/x86/kvm/vmx.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 71b2c9354423..1e2ca9e8662f 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -5012,6 +5012,8 @@ static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
 						msr, MSR_TYPE_R | MSR_TYPE_W);
 }
 
+#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
+
 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_only)
 {
 	__vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
@@ -6857,7 +6859,7 @@ static __init int hardware_setup(void)
 	set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
 
 	for (msr = 0x800; msr <= 0x8ff; msr++) {
-		if (msr == 0x839 /* TMCCT */)
+		if (msr == X2APIC_MSR(APIC_TMCCT))
 			continue;
 		vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
 	}
@@ -6866,12 +6868,9 @@ static __init int hardware_setup(void)
 	 * TPR reads and writes can be virtualized even if virtual interrupt
 	 * delivery is not in use.
 	 */
-	vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
-
-	/* EOI */
-	vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
-	/* SELF-IPI */
-	vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
+	vmx_disable_intercept_msr_x2apic(X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_R | MSR_TYPE_W, false);
+	vmx_disable_intercept_msr_x2apic(X2APIC_MSR(APIC_EOI), MSR_TYPE_W, true);
+	vmx_disable_intercept_msr_x2apic(X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W, true);
 
 	if (enable_ept)
 		vmx_enable_tdp();
@@ -10041,17 +10040,17 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
 
 	nested_vmx_disable_intercept_for_msr(
 		msr_bitmap_l1, msr_bitmap_l0,
-		APIC_BASE_MSR + (APIC_TASKPRI >> 4),
+		X2APIC_MSR(APIC_TASKPRI),
 		MSR_TYPE_W);
 
 	if (nested_cpu_has_vid(vmcs12)) {
 		nested_vmx_disable_intercept_for_msr(
 			msr_bitmap_l1, msr_bitmap_l0,
-			APIC_BASE_MSR + (APIC_EOI >> 4),
+			X2APIC_MSR(APIC_EOI),
 			MSR_TYPE_W);
 		nested_vmx_disable_intercept_for_msr(
 			msr_bitmap_l1, msr_bitmap_l0,
-			APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
+			X2APIC_MSR(APIC_SELF_IPI),
 			MSR_TYPE_W);
 	}
 	kunmap(page);
--
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