powerpc/mm: Flush radix process translations when setting MMU type

"Linux Kernel Mailing List" <[email protected]> Wed, 14 Feb 2018 18:19:53 +0000 (UTC)
Newsgroups gmane.linux.kernel.commits.head
Message-ID <[email protected]>
Web:        https://git.kernel.org/torvalds/c/62e984ddfd6b056d399e24113f5e6a7145e579d8
Commit:     62e984ddfd6b056d399e24113f5e6a7145e579d8
Parent:     b00b62898631b756c3e123542bbb0487aa343dd9
Refname:    refs/heads/master
Author:     Alexey Kardashevskiy <[email protected]>
AuthorDate: Thu Feb 1 16:09:44 2018 +1100
Committer:  Michael Ellerman <[email protected]>
CommitDate: Tue Feb 13 22:37:47 2018 +1100

    powerpc/mm: Flush radix process translations when setting MMU type
    
    Radix guests do normally invalidate process-scoped translations when a
    new pid is allocated but migrated guests do not invalidate these so
    migrated guests crash sometime, especially easy to reproduce with
    migration happening within first 10 seconds after the guest boot start
    on the same machine.
    
    This adds the "Invalidate process-scoped translations" flush to fix
    radix guests migration.
    
    Fixes: 2ee13be34b13 ("KVM: PPC: Book3S HV: Update kvmppc_set_arch_compat() for ISA v3.00")
    Cc: [email protected] # v4.10+
    Signed-off-by: Alexey Kardashevskiy <[email protected]>
    Tested-by: Laurent Vivier <[email protected]>
    Tested-by: Daniel Henrique Barboza <[email protected]>
    Signed-off-by: Michael Ellerman <[email protected]>
---
 arch/powerpc/mm/pgtable_64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index c9a623c2d8a2..d75dd5273d15 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -471,6 +471,8 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
 	if (old & PATB_HR) {
 		asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
 			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+		asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
+			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
 		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
 	} else {
 		asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
--
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