drm/i915/vlv: Add cdclk workaround for DSI

Web:        https://git.kernel.org/torvalds/c/405cacc947f7b58969b2a8ab1568c2d98b245308
Commit:     405cacc947f7b58969b2a8ab1568c2d98b245308
Parent:     a8856919432eca7b1194c89e3e5d37ce02af1519
Refname:    refs/heads/master
Author:     Hans de Goede <[email protected]>
AuthorDate: Wed Dec 20 11:50:17 2017 +0100
Committer:  Rodrigo Vivi <[email protected]>
CommitDate: Wed Feb 14 11:39:44 2018 -0800

    drm/i915/vlv: Add cdclk workaround for DSI
    
    At least on the Chuwi Vi8 (non pro/plus) the LCD panel will show an image
    shifted aprox. 20% to the left (with wraparound) and sometimes also wrong
    colors, showing that the panel controller is starting with sampling the
    datastream somewhere mid-line. This happens after the first blanking and
    re-init of the panel.
    
    After looking at drm.debug output I noticed that initially we inherit the
    cdclk of 333333 KHz set by the GOP, but after the re-init we picked 266667
    KHz, which turns out to be the cause of this problem, a quick hack to hard
    code the cdclk to 333333 KHz makes the problem go away.
    
    I've tested this on various Bay Trail devices, to make sure this not does
    cause regressions on other devices and the higher cdclk does not cause
    any problems on the following devices:
    -GP-electronic T701      1024x600   333333 KHz cdclk after this patch
    -PEAQ C1010              1920x1200  333333 KHz cdclk after this patch
    -PoV mobii-wintab-800w    800x1280  333333 KHz cdclk after this patch
    -Asus Transformer-T100TA 1368x768   320000 KHz cdclk after this patch
    
    Also interesting wrt this is the comment in vlv_calc_cdclk about the
    existing workaround to avoid 200 Mhz as clock because that causes issues
    in some cases.
    
    This commit extends the "do not use 200 Mhz" workaround with an extra
    check to require atleast 320000 KHz (avoiding 266667 KHz) when a DSI
    panel is active.
    
    Changes in v2:
    -Change the commit message and the code comment to not treat the GOP as
     a reference, the GOP should not be treated as a reference
    
    Acked-by: Ville Syrjälä <[email protected]>
    Signed-off-by: Hans de Goede <[email protected]>
    Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
    (cherry picked from commit c8dae55a8ced625038d52d26e48273707fab2688)
    Signed-off-by: Rodrigo Vivi <[email protected]>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 5dc118f26b51..1704c8897afd 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1952,6 +1952,14 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
 		min_cdclk = max(2 * 96000, min_cdclk);
 
+	/*
+	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
+	 * than 320000KHz.
+	 */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+	    IS_VALLEYVIEW(dev_priv))
+		min_cdclk = max(320000, min_cdclk);
+
 	if (min_cdclk > dev_priv->max_cdclk_freq) {
 		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
 			      min_cdclk, dev_priv->max_cdclk_freq);
--
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