arm64: Add missing Falkor part number for branch predictor hardening

Web:        https://git.kernel.org/torvalds/c/16e574d762ac5512eb922ac0ac5eed360b7db9d8
Commit:     16e574d762ac5512eb922ac0ac5eed360b7db9d8
Parent:     7928b2cbe55b2a410a0f5c1f154610059c57b1b2
Refname:    refs/heads/master
Author:     Shanker Donthineni <[email protected]>
AuthorDate: Sun Feb 11 19:16:15 2018 -0600
Committer:  Catalin Marinas <[email protected]>
CommitDate: Mon Feb 12 11:28:45 2018 +0000

    arm64: Add missing Falkor part number for branch predictor hardening
    
    References to CPU part number MIDR_QCOM_FALKOR were dropped from the
    mailing list patch due to mainline/arm64 branch dependency. So this
    patch adds the missing part number.
    
    Fixes: ec82b567a74f ("arm64: Implement branch predictor hardening for Falkor")
    Acked-by: Marc Zyngier <[email protected]>
    Signed-off-by: Shanker Donthineni <[email protected]>
    Signed-off-by: Catalin Marinas <[email protected]>
---
 arch/arm64/kernel/cpu_errata.c | 9 +++++++++
 arch/arm64/kvm/hyp/switch.c    | 4 +++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 07823595b7f0..52f15cd896e1 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -406,6 +406,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
 		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
 	},
+	{
+		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
+		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
+		.enable = qcom_enable_link_stack_sanitization,
+	},
+	{
+		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
+		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
+	},
 	{
 		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 116252a8d3a5..870f4b1587f9 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -407,8 +407,10 @@ again:
 		u32 midr = read_cpuid_id();
 
 		/* Apply BTAC predictors mitigation to all Falkor chips */
-		if ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)
+		if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
+		    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
 			__qcom_hyp_sanitize_btac_predictors();
+		}
 	}
 
 	fp_enabled = __fpsimd_enabled();
--
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