[PATCH v2 1/1] arm64: dts: st: Add I/O sync to eth1 pinctrl in stm32mp25-pinctrl.dtsi
Christophe Roullier <christophe.roullier-rj0Iel/[email protected]>
| Newsgroups | gmane.linux.drivers.devicetree,gmane.linux.ports.arm.kernel,gmane.linux.kernel |
|---|---|
| Message-ID | <[email protected]> |
On board stm32mp235f-dk, stm32mp257f-dk the propagation delay between eth1 and the external PHY requires a compensation to guarantee that no packet get lost in all the working conditions. Add I/O synchronization properties in pinctrl on all the RGMII data pins, activating re-sampling on both edges of the clock. Co-developed-by: Antonio Borneo <antonio.borneo-rj0Iel/[email protected]> Signed-off-by: Antonio Borneo <antonio.borneo-rj0Iel/[email protected]> Signed-off-by: Christophe Roullier <christophe.roullier-rj0Iel/[email protected]> --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc..4fcfc4528c5e 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -95,6 +95,7 @@ pins1 { bias-disable; drive-push-pull; slew-rate = <3>; + st,io-sync = "data on both edges"; }; pins2 { pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ @@ -112,6 +113,7 @@ pins3 { <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ bias-disable; + st,io-sync = "data on both edges"; }; pins4 { pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ -- 2.43.0