[tip: locking/core] arm64: sched/preempt: Enable HAS_SEPARATE_PREEMPT_RESCHED_BITS
"tip-bot2 for Boqun Feng" <[email protected]>
| Newsgroups | gmane.linux.kernel |
|---|---|
| Message-ID | <178622210298.442315.16258034056736598907.tip-bot2@tip-bot2> |
The following commit has been merged into the locking/core branch of tip: Commit-ID: c9bae17d96b93ce05ff2eeef08165c24c7f5e7e3 Gitweb: https://git.kernel.org/tip/c9bae17d96b93ce05ff2eeef08165c24c7f5e7e3 Author: Boqun Feng <[email protected]> AuthorDate: Tue, 04 Aug 2026 09:14:33 -07:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Sat, 08 Aug 2026 22:44:08 +02:00 arm64: sched/preempt: Enable HAS_SEPARATE_PREEMPT_RESCHED_BITS Arm64 already uses 64-bit preempt count and the need reschedule bit is maintained in a separate 32-bit word from the preempt count. Therefore preempt count has enough bits to represent 16 levels of NMI nesting, hence enable it for arm64. This saves a per-CPU variable and additional instructions in the NMI path. Signed-off-by: Boqun Feng <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://patch.msgid.link/[email protected] --- arch/arm64/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b3afe06..349c353 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -247,6 +247,7 @@ config ARM64 select PCI_SYSCALL if PCI select POWER_RESET select POWER_SUPPLY + select HAS_SEPARATE_PREEMPT_RESCHED_BITS select SPARSE_IRQ select SWIOTLB select SYSCTL_EXCEPTION_TRACE