[PATCH v5 06/15] crypto: ti - Align buffers to cacheline for DMA
T Pratham <[email protected]>
| Newsgroups | gmane.linux.kernel,gmane.linux.kernel.cryptoapi |
|---|---|
| Message-ID | <[email protected]> |
Align padding buffer which are DMA mapped to cache line to avoid any
potential cache coherence problem.
Fixes: 35645ca63caa1 ("crypto: ti - Add support for AES-CTR in DTHEv2 driver")
Signed-off-by: T Pratham <[email protected]>
---
drivers/crypto/ti/dthev2-common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-common.h
index a827817e8119a..cfb50255a5dce 100644
--- a/drivers/crypto/ti/dthev2-common.h
+++ b/drivers/crypto/ti/dthev2-common.h
@@ -114,7 +114,9 @@ struct dthe_tfm_ctx {
*/
struct dthe_aes_req_ctx {
int enc;
+ __dma_from_device_group_begin();
u8 padding[2 * AES_BLOCK_SIZE];
+ __dma_from_device_group_end();
struct completion aes_compl;
struct dthe_data *dev_data;
};
--
2.34.1