Re: [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs
Brian Masney <[email protected]>
| Newsgroups | gmane.linux.kernel.clk,gmane.linux.drivers.devicetree,gmane.linux.kernel,gmane.linux.ports.arm.kernel,gmane.linux.ports.arm.mediatek,gmane.linux.network |
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| Message-ID | <[email protected]> |
On Sat, Aug 01, 2026 at 01:21:01PM +0200, Louis-Alexis Eyraud wrote: > Add new set of PLL FHCTL clock operations, that uses the new prepare > and unprepare methods, added in PLL for MT8189 SoC to support this > logic. > > Signed-off-by: Louis-Alexis Eyraud <[email protected]> Reviewed-by: Brian Masney <[email protected]>