Re: [PATCH 1/2] Add oprofile support for ARM Cortex A57 microarchitecture

Maynard Johnson <[email protected]>
Newsgroups gmane.linux.oprofile
Message-ID <[email protected]> 
*Will Deacon* ... Can you please give your blessing to this patch, as well as to the "PATCH 2/2 Add oprofile support for ARM Cortex A53 microarchitecture".  Thanks.

-Maynard



On 07/21/2014 02:29 PM, William Cohen wrote:
> This patch adds the event list of the ARM Cortex A57 architecture.
> 
> The patch is very straight forward: just add the model numbers and
> type in the usual places and add the event list.
> 
> Passes make check
> 
> Signed-off-by: William Cohen <[email protected]>
> ---
>  events/Makefile.am               |  1 +
>  events/arm/armv8-ca57/events     | 67 ++++++++++++++++++++++++++++++++++++++++
>  events/arm/armv8-ca57/unit_masks |  3 ++
>  libop/op_cpu_type.c              |  3 ++
>  libop/op_cpu_type.h              |  1 +
>  libop/op_events.c                |  1 +
>  utils/ophelp.c                   |  6 ++++
>  7 files changed, 82 insertions(+)
>  create mode 100644 events/arm/armv8-ca57/events
>  create mode 100644 events/arm/armv8-ca57/unit_masks
> 
> diff --git a/events/Makefile.am b/events/Makefile.am
> index f6fd3d7..b4bca1e 100644
> --- a/events/Makefile.am
> +++ b/events/Makefile.am
> @@ -62,6 +62,7 @@ event_files = \
>  	arm/mpcore/events arm/mpcore/unit_masks \
>  	arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \
>  	arm/armv8-xgene/events arm/armv8-xgene/unit_masks \
> +	arm/armv8-ca57/events arm/armv8-ca57/unit_masks \
>  	avr32/events avr32/unit_masks \
>  	mips/20K/events mips/20K/unit_masks \
>  	mips/24K/events mips/24K/unit_masks \
> diff --git a/events/arm/armv8-ca57/events b/events/arm/armv8-ca57/events
> new file mode 100644
> index 0000000..62974c1
> --- /dev/null
> +++ b/events/arm/armv8-ca57/events
> @@ -0,0 +1,67 @@
> +#
> +# Copyright (c) Red Hat, 2014.
> +# Contributed by William Cohen <[email protected]>
> +#
> +# ARM Cortex A57 events
> +# From Cortex A57 TRM
> +#
> +include:arm/armv8-pmuv3-common
> +event:0x40 um:zero minimum:10007 name:L1D_CACHE_LD : Level 1 data cache access - Read
> +event:0x41 um:zero minimum:10007 name:L1D_CACHE_ST : Level 1 data cache access - Write
> +event:0x42 um:zero minimum:10007 name:L1D_CACHE_REFILL_LD : Level 1 data cache refill - Read
> +event:0x43 um:zero minimum:10007 name:L1D_CACHE_REFILL_ST : Level 1 data cache refill - Write
> +event:0x46 um:zero minimum:10007 name:L1D_CACHE_WB_VICTIM : Level 1 data cache Write-back - Victim
> +event:0x47 um:zero minimum:10007 name:L1D_CACHE_WB_CLEAN : Level 1 data cache Write-back - Cleaning event:and coherency
> +event:0x48 um:zero minimum:10007 name:L1D_CACHE_INVAL : Level 1 data cache invalidate
> +event:0x4C um:zero minimum:10007 name:L1D_TLB_REFILL_LD : Level 1 data TLB refill - Read
> +event:0x4D um:zero minimum:10007 name:L1D_TLB_REFILL_ST : Level 1 data TLB refill - Write
> +event:0x50 um:zero minimum:10007 name:L2D_CACHE_LD : Level 2 data cache access - Read
> +event:0x51 um:zero minimum:10007 name:L2D_CACHE_ST : Level 2 data cache access - Write
> +event:0x52 um:zero minimum:10007 name:L2D_CACHE_REFILL_LD : Level 2 data cache refill - Read
> +event:0x53 um:zero minimum:10007 name:L2D_CACHE_REFILL_ST : Level 2 data cache refill - Write
> +event:0x56 um:zero minimum:10007 name:L2D_CACHE_WB_VICTIM : Level 2 data cache Write-back - Victim
> +event:0x57 um:zero minimum:10007 name:L2D_CACHE_WB_CLEAN : Level 2 data cache Write-back - Cleaning and coherency
> +event:0x58 um:zero minimum:10007 name:L2D_CACHE_INVAL : Level 2 data cache invalidate
> +event:0x60 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read
> +event:0x61 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write
> +event:0x62 um:zero minimum:10007 name:BUS_ACCESS_SHARED : Bus access - Normal
> +event:0x63 um:zero minimum:10007 name:BUS_ACCESS_NOT_SHARED : Bus access - Not normal
> +event:0x64 um:zero minimum:10007 name:BUS_ACCESS_NORMAL : Bus access - Normal
> +event:0x65 um:zero minimum:10007 name:BUS_ACCESS_PERIPH : Bus access - Peripheral
> +event:0x66 um:zero minimum:10007 name:MEM_ACCESS_LD : Data memory access - Read
> +event:0x67 um:zero minimum:10007 name:MEM_ACCESS_ST : Data memory access - Write
> +event:0x68 um:zero minimum:10007 name:UNALIGNED_LD_SPEC : Unaligned access - Read
> +event:0x69 um:zero minimum:10007 name:UNALIGNED_ST_SPEC : Unaligned access - Write
> +event:0x6A um:zero minimum:10007 name:UNALIGNED_LDST_SPEC : Unaligned access
> +event:0x6C um:zero minimum:10007 name:LDREX_SPEC : Exclusive operation speculatively executed - LDREX
> +event:0x6D um:zero minimum:10007 name:STREX_PASS_SPEC : Exclusive instruction speculatively executed - STREX pass
> +event:0x6E um:zero minimum:10007 name:STREX_FAIL_SPEC : Exclusive operation speculatively executed - STREX fail
> +event:0x70 um:zero minimum:10007 name:LD_SPEC : Operation speculatively executed - Load
> +event:0x71 um:zero minimum:10007 name:ST_SPEC : Operation speculatively executed - Store
> +event:0x72 um:zero minimum:10007 name:LDST_SPEC : Operation speculatively executed - Load or store
> +event:0x73 um:zero minimum:10007 name:DP_SPEC : Operation speculatively executed - Integer data processing
> +event:0x74 um:zero minimum:10007 name:ASE_SPEC : Operation speculatively executed - Advanced SIMD
> +event:0x75 um:zero minimum:10007 name:VFP_SPEC : Operation speculatively executed - VFP
> +event:0x76 um:zero minimum:10007 name:PC_WRITE_SPEC : Operation speculatively executed - Software change of the PC
> +event:0x77 um:zero minimum:10007 name:CRYPTO_SPEC : Operation speculatively executed, crypto data processing
> +event:0x78 um:zero minimum:10007 name:BR_IMMED_SPEC : Branch speculatively executed - Immediate branch
> +event:0x79 um:zero minimum:10007 name:BR_RETURN_SPEC : Branch speculatively executed - Procedure return
> +event:0x7A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculatively executed - Indirect branch
> +event:0x7C um:zero minimum:10007 name:ISB_SPEC : Barrier speculatively executed - ISB
> +event:0x7D um:zero minimum:10007 name:DSB_SPEC : Barrier speculatively executed - DSB
> +event:0x7E um:zero minimum:10007 name:DMB_SPEC : Barrier speculatively executed - DMB
> +event:0x81 um:zero minimum:10007 name:EXC_UNDEF : Exception taken, other synchronous
> +event:0x82 um:zero minimum:10007 name:EXC_SVC : Exception taken, Supervisor Call
> +event:0x83 um:zero minimum:10007 name:EXC_PABORT : Exception taken, Instruction Abort
> +event:0x84 um:zero minimum:10007 name:EXC_DABORT : Exception taken, Data Abort or SError
> +event:0x86 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ
> +event:0x87 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ
> +event:0x88 um:zero minimum:10007 name:EXC_SMC : Exception taken, Secure Monitor Call
> +event:0x8A um:zero minimum:10007 name:EXC_HVC : Exception taken, Hypervisor Call
> +event:0x8B um:zero minimum:10007 name:EXC_TRAP_PABORT : Exception taken, Instruction Abort not taken locally
> +event:0x8C um:zero minimum:10007 name:EXC_TRAP_DABORT : Exception taken, Data Abort, or SError not taken locally
> +event:0x8D um:zero minimum:10007 name:EXC_TRAP_OTHER : Exception taken – Other traps not taken locally
> +event:0x8E um:zero minimum:10007 name:EXC_TRAP_IRQ : Exception taken, IRQ not taken locally
> +event:0x8F um:zero minimum:10007 name:EXC_TRAP_FIQ : Exception taken, FIQ not taken locally
> +event:0x90 um:zero minimum:10007 name:RC_LD_SPEC : Release consistency instruction speculatively executed – Load-Acquire
> +event:0x91 um:zero minimum:10007 name:RC_ST_SPEC : Release consistency instruction speculatively executed – Store-Release
> diff --git a/events/arm/armv8-ca57/unit_masks b/events/arm/armv8-ca57/unit_masks
> new file mode 100644
> index 0000000..5d69263
> --- /dev/null
> +++ b/events/arm/armv8-ca57/unit_masks
> @@ -0,0 +1,3 @@
> +# ARMv8 Cortex A57 unit masks
> +#
> +include:arm/armv8-pmuv3-common
> diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c
> index bce230a..163bd1c 100644
> --- a/libop/op_cpu_type.c
> +++ b/libop/op_cpu_type.c
> @@ -131,6 +131,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {
>  	{ "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 },
>  	{ "APM X-Gene", "arm/armv8-xgene", CPU_ARM_V8_APM_XGENE, 6 },
>  	{ "Intel Broadwell microarchitecture", "i386/broadwell", CPU_BROADWELL, 4 },
> +	{ "ARM Cortex-A57", "arm/armv8-ca57", CPU_ARM_V8_CA57, 6},
>  };
>   
>  static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
> @@ -396,6 +397,8 @@ static op_cpu _get_arm_cpu_type(void)
>  			return op_get_cpu_number("arm/armv7-ca9");
>  		case 0xc0f:
>  			return op_get_cpu_number("arm/armv7-ca15");
> +		case 0xd07:
> +			return op_get_cpu_number("arm/armv8-ca57");
>  		}
>  	} else if (vendorid == 0x50) {	/* Applied Micro Circuits Corporation */
>  		switch (cpuid) {
> diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h
> index 3754156..aebd7f6 100644
> --- a/libop/op_cpu_type.h
> +++ b/libop/op_cpu_type.h
> @@ -111,6 +111,7 @@ typedef enum {
>  	CPU_ARM_KRAIT, /**< ARM KRAIT */
>  	CPU_ARM_V8_APM_XGENE, /* APM X-Gene */
>  	CPU_BROADWELL, /** < Intel Broadwell (Core-M) microarchitecture */
> +	CPU_ARM_V8_CA57, /* ARM Cortex-A57 */
>  	MAX_CPU_TYPE
>  } op_cpu;
>  
> diff --git a/libop/op_events.c b/libop/op_events.c
> index b8900a5..d5249b7 100644
> --- a/libop/op_events.c
> +++ b/libop/op_events.c
> @@ -1255,6 +1255,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)
>  		case CPU_ARM_SCORPIONMP:
>  		case CPU_ARM_KRAIT:
>  		case CPU_ARM_V8_APM_XGENE:
> +		case CPU_ARM_V8_CA57:
>  			descr->name = "CPU_CYCLES";
>  			break;
>  
> diff --git a/utils/ophelp.c b/utils/ophelp.c
> index bf3fbcb..a5edf56 100644
> --- a/utils/ophelp.c
> +++ b/utils/ophelp.c
> @@ -664,6 +664,12 @@ int main(int argc, char const * argv[])
>  			"DDI (ARM DDI0487A.a)\n";
>  		break;
>  
> +	case CPU_ARM_V8_CA57:
> +		event_doc =
> +			"See Cortex-A57 MPCore Technical Reference Manual\n"
> +			"Cortex A57 DDI (ARM DDI 0488D, revision r1p1)\n";
> +		break;
> +
>  	case CPU_PPC64_PA6T:
>  		event_doc =
>  			"See PA6T Power Implementation Features Book IV\n"
> 


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