Re: [PATCH 2/2] Add oprofile support for ARM Cortex A53 microarchitecture
William Cohen <[email protected]>
| Newsgroups | gmane.linux.oprofile |
|---|---|
| Message-ID | <[email protected]> |
On 07/23/2014 04:33 AM, Will Deacon wrote: > On Mon, Jul 21, 2014 at 08:29:20PM +0100, William Cohen wrote: >> This patch adds the event list of the ARM Cortex A53 architecture. >> >> The patch is very straight forward: just add the model numbers and >> type in the usual places and add the event list. >> >> Passes make check >> >> Signed-off-by: William Cohen <[email protected]> >> --- >> events/Makefile.am | 1 + >> events/arm/armv8-ca53/events | 13 ++++++++ >> events/arm/armv8-ca53/events~ | 67 ++++++++++++++++++++++++++++++++++++++++ > > Did you mean to include both of these files in the patch? > > Will > Hi Will, Thanks for catching that. Attached is revised patch that has events~ removed. -Will ------------------------------------------------------------------------------ Want fast and easy access to all the code in your enterprise? Index and search up to 200,000 lines of code with a free copy of Black Duck Code Sight - the same software that powers the world's largest code search on Ohloh, the Black Duck Open Hub! Try it now. http://p.sf.net/sfu/bds _______________________________________________ oprofile-list mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/oprofile-list
0001-Add-oprofile-support-for-ARM-Cortex-A53-microarchite.patch
(text/x-patch, 4.5 KB)
>From d3c42be8818465cbaabae9dda08f7345ddcbe7eb Mon Sep 17 00:00:00 2001 From: William Cohen <[email protected]> Date: Wed, 23 Jul 2014 11:36:37 -0400 Subject: [PATCH] Add oprofile support for ARM Cortex A53 microarchitecture This patch adds the event list of the ARM Cortex A53 architecture. The patch is very straight forward: just add the model numbers and type in the usual places and add the event list. Passes make check Signed-off-by: William Cohen <[email protected]> --- events/Makefile.am | 1 + events/arm/armv8-ca53/events | 13 +++++++++++++ events/arm/armv8-ca53/unit_masks | 3 +++ libop/op_cpu_type.c | 3 +++ libop/op_cpu_type.h | 1 + libop/op_events.c | 1 + utils/ophelp.c | 6 ++++++ 7 files changed, 28 insertions(+) create mode 100644 events/arm/armv8-ca53/events create mode 100644 events/arm/armv8-ca53/unit_masks diff --git a/events/Makefile.am b/events/Makefile.am index b4bca1e..67be125 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -63,6 +63,7 @@ event_files = \ arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \ arm/armv8-xgene/events arm/armv8-xgene/unit_masks \ arm/armv8-ca57/events arm/armv8-ca57/unit_masks \ + arm/armv8-ca53/events arm/armv8-ca53/unit_masks \ avr32/events avr32/unit_masks \ mips/20K/events mips/20K/unit_masks \ mips/24K/events mips/24K/unit_masks \ diff --git a/events/arm/armv8-ca53/events b/events/arm/armv8-ca53/events new file mode 100644 index 0000000..b5c171f --- /dev/null +++ b/events/arm/armv8-ca53/events @@ -0,0 +1,13 @@ +# +# Copyright (c) Red Hat, 2014. +# Contributed by William Cohen <[email protected]> +# +# ARM Cortex A53 events +# From Cortex A53 TRM +# +include:arm/armv8-pmuv3-common +event:0x60 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read. +event:0x61 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write. +event:0x7A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculatively executed - Indirect branch. +event:0x86 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ. +event:0x87 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ. diff --git a/events/arm/armv8-ca53/unit_masks b/events/arm/armv8-ca53/unit_masks new file mode 100644 index 0000000..5d69263 --- /dev/null +++ b/events/arm/armv8-ca53/unit_masks @@ -0,0 +1,3 @@ +# ARMv8 Cortex A57 unit masks +# +include:arm/armv8-pmuv3-common diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index 163bd1c..055c64b 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -132,6 +132,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "APM X-Gene", "arm/armv8-xgene", CPU_ARM_V8_APM_XGENE, 6 }, { "Intel Broadwell microarchitecture", "i386/broadwell", CPU_BROADWELL, 4 }, { "ARM Cortex-A57", "arm/armv8-ca57", CPU_ARM_V8_CA57, 6}, + { "ARM Cortex-A53", "arm/armv8-ca53", CPU_ARM_V8_CA53, 6}, }; static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); @@ -399,6 +400,8 @@ static op_cpu _get_arm_cpu_type(void) return op_get_cpu_number("arm/armv7-ca15"); case 0xd07: return op_get_cpu_number("arm/armv8-ca57"); + case 0xd03: + return op_get_cpu_number("arm/armv8-ca53"); } } else if (vendorid == 0x50) { /* Applied Micro Circuits Corporation */ switch (cpuid) { diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index aebd7f6..a6bb323 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -112,6 +112,7 @@ typedef enum { CPU_ARM_V8_APM_XGENE, /* APM X-Gene */ CPU_BROADWELL, /** < Intel Broadwell (Core-M) microarchitecture */ CPU_ARM_V8_CA57, /* ARM Cortex-A57 */ + CPU_ARM_V8_CA53, /* ARM Cortex-A53 */ MAX_CPU_TYPE } op_cpu; diff --git a/libop/op_events.c b/libop/op_events.c index d5249b7..bbeb212 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1256,6 +1256,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) case CPU_ARM_KRAIT: case CPU_ARM_V8_APM_XGENE: case CPU_ARM_V8_CA57: + case CPU_ARM_V8_CA53: descr->name = "CPU_CYCLES"; break; diff --git a/utils/ophelp.c b/utils/ophelp.c index a5edf56..980c6dc 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -670,6 +670,12 @@ int main(int argc, char const * argv[]) "Cortex A57 DDI (ARM DDI 0488D, revision r1p1)\n"; break; + case CPU_ARM_V8_CA53: + event_doc = + "See Cortex-A53 MPCore Technical Reference Manual\n" + "Cortex A57 DDI (ARM DDI 0500D, revision r0p2)\n"; + break; + case CPU_PPC64_PA6T: event_doc = "See PA6T Power Implementation Features Book IV\n" -- 1.9.3