Re: [PATCH 2/2] Add oprofile support for ARM Cortex A53 microarchitecture

Will Deacon <[email protected]>
Newsgroups gmane.linux.oprofile
Message-ID <[email protected]> 
On Thu, Jul 24, 2014 at 04:30:08AM +0100, William Cohen wrote:
> On 07/23/2014 12:22 PM, Will Deacon wrote:
> > On Wed, Jul 23, 2014 at 04:39:32PM +0100, William Cohen wrote:
> >> +event:0x61 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write.
> >> +event:0x7A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculatively executed - Indirect branch.
> >> +event:0x86 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ.
> >> +event:0x87 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ.
> > 
> > A53 has a bunch more events listed in the TRM, they just don't have catchy
> > mnemonics.
> 
> The attached version of the patch has added names for the other events
> listed in the a53 TRM.  I tried to match them up with events from other
> arm processors where possible.  However, some of the names could be
> better.
> 
> > 
> >> diff --git a/events/arm/armv8-ca53/unit_masks b/events/arm/armv8-ca53/unit_masks
> >> new file mode 100644
> >> index 0000000..5d69263
> >> --- /dev/null
> >> +++ b/events/arm/armv8-ca53/unit_masks
> >> @@ -0,0 +1,3 @@
> >> +# ARMv8 Cortex A57 unit masks
> > 
> > s/A57/A53/
> 
> Changed to A53.

Thanks, Will. The revised patch looks good to me (thinking up those
mnemonics always takes longer than it should).

  Reviewed-by: Will Deacon <[email protected]>

Will

> -Will

> From 78db0d3eb65e6005931b0402484e759c35df79f1 Mon Sep 17 00:00:00 2001
> From: William Cohen <[email protected]>
> Date: Wed, 23 Jul 2014 23:25:21 -0400
> Subject: [PATCH] Add oprofile support for ARM Cortex A53 microarchitecture
> 
> This patch adds the event list of the ARM Cortex A53 architecture.
> 
> The patch is very straight forward: just add the model numbers and
> type in the usual places and add the event list.
> 
> Passes make check
> 
> Signed-off-by: William Cohen <[email protected]>
> ---
>  events/Makefile.am               |  1 +
>  events/arm/armv8-ca53/events     | 38 ++++++++++++++++++++++++++++++++++++++
>  events/arm/armv8-ca53/unit_masks |  3 +++
>  libop/op_cpu_type.c              |  3 +++
>  libop/op_cpu_type.h              |  1 +
>  libop/op_events.c                |  1 +
>  utils/ophelp.c                   |  6 ++++++
>  7 files changed, 53 insertions(+)
>  create mode 100644 events/arm/armv8-ca53/events
>  create mode 100644 events/arm/armv8-ca53/unit_masks
> 
> diff --git a/events/Makefile.am b/events/Makefile.am
> index b4bca1e..67be125 100644
> --- a/events/Makefile.am
> +++ b/events/Makefile.am
> @@ -63,6 +63,7 @@ event_files = \
>  	arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \
>  	arm/armv8-xgene/events arm/armv8-xgene/unit_masks \
>  	arm/armv8-ca57/events arm/armv8-ca57/unit_masks \
> +	arm/armv8-ca53/events arm/armv8-ca53/unit_masks \
>  	avr32/events avr32/unit_masks \
>  	mips/20K/events mips/20K/unit_masks \
>  	mips/24K/events mips/24K/unit_masks \
> diff --git a/events/arm/armv8-ca53/events b/events/arm/armv8-ca53/events
> new file mode 100644
> index 0000000..5e1b4d8
> --- /dev/null
> +++ b/events/arm/armv8-ca53/events
> @@ -0,0 +1,38 @@
> +#
> +# Copyright (c) Red Hat, 2014.
> +# Contributed by William Cohen <[email protected]>
> +#
> +# ARM Cortex A53 events
> +# From Cortex A53 TRM
> +#
> +include:arm/armv8-pmuv3-common
> +event:0x60 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read
> +event:0x61 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write
> +event:0x7A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculatively executed - Indirect branch
> +event:0x86 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ
> +event:0x87 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ
> +event:0xC0 um:zero minimum:10007 name:EXT_MEM_REQ : External memory request
> +event:0xC1 um:zero minimum:10007 name:EXT_MEM_REQ_NC : Non-cacheable external memory request
> +event:0xC2 um:zero minimum:10007 name:PREFETCH_LINEFILL : Linefill because of prefetch
> +event:0xC3 um:zero minimum:10007 name:PREFETCH_LINEFILL_DROP : Instruction Cache Throttle occurred
> +event:0xC4 um:zero minimum:10007 name:READ_ALLOC_ENTER : Entering read allocate mode
> +event:0xC5 um:zero minimum:10007 name:READ_ALLOC : Read allocate mode
> +event:0xC6 um:zero minimum:10007 name:PRE_DECODE_ERR : Pre-decode error
> +event:0xC7 um:zero minimum:10007 name:STALL_SB_FULL : Data Write operation that stalls the pipeline because the store buffer is full
> +event:0xC8 um:zero minimum:10007 name:EXT_SNOOP : SCU Snooped data from another CPU for this CPU
> +event:0xC9 um:zero minimum:10007 name:BR_COND : Conditional branch executed
> +event:0xCA um:zero minimum:10007 name:BR_INDIRECT_MISPRED : Indirect branch mispredicted
> +event:0xCB um:zero minimum:10007 name:BR_INDIRECT_MISPRED_ADDR : Indirect branch mispredicted because of address miscompare
> +event:0xCC um:zero minimum:10007 name:BR_COND_MISPRED : Conditional branch mispredicted
> +event:0xD0 um:zero minimum:10007 name:L1I_CACHE_ERR : L1 Instruction Cache (data or tag) memory error
> +event:0xD1 um:zero minimum:10007 name:L1D_CACHE_ERR : L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable
> +event:0xD2 um:zero minimum:10007 name:TLB_ERR : TLB memory error
> +event:0xE0 um:zero minimum:10007 name:OTHER_IQ_DEP_STALL : Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error
> +event:0xE1 um:zero minimum:10007 name:IC_DEP_STALL : Cycles the DPU IQ is empty and there is an instruction cache miss being processed
> +event:0xE2 um:zero minimum:10007 name:IUTLB_DEP_STALL : Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed
> +event:0xE3 um:zero minimum:10007 name:DECODE_DEP_STALL : Cycles the DPU IQ is empty and there is a pre-decode error being processed
> +event:0xE4 um:zero minimum:10007 name:OTHER_INTERLOCK_STALL : Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction
> +event:0xE5 um:zero minimum:10007 name:AGU_DEP_STALL : Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU
> +event:0xE6 um:zero minimum:10007 name:SIMD_DEP_STALL : Cycles there is an interlock for an Advanced SIMD/Floating-point operation.
> +event:0xE7 um:zero minimum:10007 name:LD_DEP_STALL : Cycles there is a stall in the Wr stage because of a load miss
> +event:0xE8 um:zero minimum:10007 name:ST_DEP_STALL : Cycles there is a stall in the Wr stage because of a store
> diff --git a/events/arm/armv8-ca53/unit_masks b/events/arm/armv8-ca53/unit_masks
> new file mode 100644
> index 0000000..42b12b4
> --- /dev/null
> +++ b/events/arm/armv8-ca53/unit_masks
> @@ -0,0 +1,3 @@
> +# ARMv8 Cortex A53 unit masks
> +#
> +include:arm/armv8-pmuv3-common
> diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c
> index 163bd1c..055c64b 100644
> --- a/libop/op_cpu_type.c
> +++ b/libop/op_cpu_type.c
> @@ -132,6 +132,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {
>  	{ "APM X-Gene", "arm/armv8-xgene", CPU_ARM_V8_APM_XGENE, 6 },
>  	{ "Intel Broadwell microarchitecture", "i386/broadwell", CPU_BROADWELL, 4 },
>  	{ "ARM Cortex-A57", "arm/armv8-ca57", CPU_ARM_V8_CA57, 6},
> +	{ "ARM Cortex-A53", "arm/armv8-ca53", CPU_ARM_V8_CA53, 6},
>  };
>   
>  static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
> @@ -399,6 +400,8 @@ static op_cpu _get_arm_cpu_type(void)
>  			return op_get_cpu_number("arm/armv7-ca15");
>  		case 0xd07:
>  			return op_get_cpu_number("arm/armv8-ca57");
> +		case 0xd03:
> +			return op_get_cpu_number("arm/armv8-ca53");
>  		}
>  	} else if (vendorid == 0x50) {	/* Applied Micro Circuits Corporation */
>  		switch (cpuid) {
> diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h
> index aebd7f6..a6bb323 100644
> --- a/libop/op_cpu_type.h
> +++ b/libop/op_cpu_type.h
> @@ -112,6 +112,7 @@ typedef enum {
>  	CPU_ARM_V8_APM_XGENE, /* APM X-Gene */
>  	CPU_BROADWELL, /** < Intel Broadwell (Core-M) microarchitecture */
>  	CPU_ARM_V8_CA57, /* ARM Cortex-A57 */
> +	CPU_ARM_V8_CA53, /* ARM Cortex-A53 */
>  	MAX_CPU_TYPE
>  } op_cpu;
>  
> diff --git a/libop/op_events.c b/libop/op_events.c
> index d5249b7..bbeb212 100644
> --- a/libop/op_events.c
> +++ b/libop/op_events.c
> @@ -1256,6 +1256,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)
>  		case CPU_ARM_KRAIT:
>  		case CPU_ARM_V8_APM_XGENE:
>  		case CPU_ARM_V8_CA57:
> +		case CPU_ARM_V8_CA53:
>  			descr->name = "CPU_CYCLES";
>  			break;
>  
> diff --git a/utils/ophelp.c b/utils/ophelp.c
> index a5edf56..980c6dc 100644
> --- a/utils/ophelp.c
> +++ b/utils/ophelp.c
> @@ -670,6 +670,12 @@ int main(int argc, char const * argv[])
>  			"Cortex A57 DDI (ARM DDI 0488D, revision r1p1)\n";
>  		break;
>  
> +	case CPU_ARM_V8_CA53:
> +		event_doc =
> +			"See Cortex-A53 MPCore Technical Reference Manual\n"
> +			"Cortex A57 DDI (ARM DDI 0500D, revision r0p2)\n";
> +		break;
> +
>  	case CPU_PPC64_PA6T:
>  		event_doc =
>  			"See PA6T Power Implementation Features Book IV\n"
> -- 
> 1.9.3


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