Re: Perf event setup failed

On 05/05/2015 03:53 PM, Mike Accola wrote:
> Perf doesn't like the r04c5:pp event on this machine:
> 
> maccola@h0817:/tmp> perf stat -e r04c5:pp ./something
> 
>  Performance counter stats for './something':
> 
>    <not supported> r04c5:pp                
> 
>        0.001229172 seconds time elapsed

Hi Mike,

As an additional datapoint you should try to see if the precise sampling is causing the issue:

perf stat -e r04c5 ./something

I suspect that the kernel checks are not allow precise sampling on that particular event.  In the git kernel I see some constraints for hsw:

http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/x86/kernel/cpu/perf_event_intel_ds.c#n647

I think that you need a newer kernel. In the 2.6.32-431.el6 kernel I don't see a similar table for haswell, but I do see that table in in rhel6.7 linux-2.6.32-504.16.2.el6 kernel (and an entry for 04c5):


struct event_constraint intel_hsw_pebs_event_constraints[] = {
	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
	INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
	INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
	INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
	INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
	INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
	INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
	INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.* */
	/* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
	INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
	/* MEM_UOPS_RETIRED.STLB_MISS_STORES */
	INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
	INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
	INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
	/* MEM_UOPS_RETIRED.SPLIT_STORES */
	INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
	INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
	INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
	INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
	INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
	INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
	/* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
	INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
	/* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
	INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
	/* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
	INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
	/* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
	INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
	INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
	INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */

	EVENT_CONSTRAINT_END
};

-Will

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