Modifying MSR has no effect on the stats

Mahmood N <[email protected]>
Newsgroups gmane.linux.oprofile
Message-ID <[email protected]>
Hi,According to the BKDG of 15h family, the following MSR controls the hardware prefetcher at L1.
MSRC001_1022 Data Cache Configuration (DC_CFG)
Bits       ///////     Description
63:16    ///////  Reserved.
15    ///////  DisPfHwForSw. Read-write. Reset: 0. 1=Disable hardware prefetches for software prefetches.
14    ///////  Reserved.
13    ///////  DisHwPf. Read-write. Reset: 0. 1=Disable the DC hardware prefetcher. BIOS: See 2.3.3 [Using L2 Cache as General Storage During Boot].
12:10    ///////  Reserved.
9:5    ///////  Reserved.
4    ///////  DisSpecTlbRld. Read-write. Reset: 0. 1=Disable speculative TLB reloads. BIOS: See 2.3.3 [UsingL2 Cache as General Storage During Boot].
3:0    ///////  Reserved.

Problem is when I disable it (setting 13th to 1), the stats regarding the prefetcher remains non-zero! 





[root@tiger exe]# rdmsr -a -x -0 0xc0011022
0000000000000000    <32 LINES FOR 32 CORES>
[root@tiger exe]# wrmsr -a 0xc0011022 0x2000
[root@tiger exe]# rdmsr -a -x -0 0xc0011022
0000000000002000   <32 LINES FOR 32 CORES>[root@tiger exe]# ocount -e CPU_CLK_UNHALTED,RETIRED_INSTRUCTIONS,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES,DATA_PREFETCHER,PREFETCH_INSTRUCTIONS_DISPATCHED,REQUESTS_TO_L2,L2_CACHE_MISS,L2_PREFETCHER_TRIGGER ./bzip2_base.amd64-m64-gcc44-nn
Events were actively counted for 36.0 seconds.
Event counts (scaled) for /home/mahmood/spec-cpu2006-x86_64/benchspec/CPU2006/401.bzip2/exe/bzip2_base.amd64-m64-gcc44-nn:
        Event                                    Count                    % time counted
        CPU_CLK_UNHALTED                         107,340,837,082          55.55
        DATA_CACHE_ACCESSES                      55,973,655,378           66.66
        DATA_CACHE_MISSES                        1,720,001,433            66.65
        DATA_PREFETCHER                          1,081,055,468            66.66
        L2_CACHE_MISS                            265,881,095              66.67
        L2_PREFETCHER_TRIGGER                    261,646,431              55.57
        PREFETCH_INSTRUCTIONS_DISPATCHED         397,803                  66.68
        REQUESTS_TO_L2                           2,796,342,677            44.45
        RETIRED_INSTRUCTIONS                     108,589,570,814          55.57





 Isn't that strange? 


Regards,
Mahmood

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