opannotate -s -i example AND duplicated ophelp output on ARM Cortex-A7 MPCore
Panagiotis Mousouliotis <[email protected]>
| Newsgroups | gmane.linux.oprofile |
|---|---|
| Message-ID | <CAONfH=O82F=xKVOUSwgFri3aVtc6VJmFyb7tTfSQgBTWW1F9Gg@mail.gmail.com> |
Hello all,
I'm using the latest version of oprofile (1.1.0).
I would like to get source code details for a specific symbol using
"opannotate -s -i <symbol>", but it seems that I can't get it right.
e.g.
$ opreport -g -l -t 1
Using
/home/pmousoul/Downloads/opencv3/opencv/build/bin/oprofile_data/samples/
for samples directory.
WARNING! Some of the events were throttled. Throttling occurs when
the initial sample rate is too high, causing an excessive number of
interrupts. Decrease the sampling frequency. Check the directory
/home/pmousoul/Downloads/opencv3/opencv/build/bin/oprofile_data/samples/current/stats/throttled
for the throttled event names.
CPU: Intel Ivy Bridge microarchitecture, speed 2700 MHz (estimated)
Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a unit
mask of 0x00 (No unit mask) count 90000
warning: some functions compiled without debug information may have
incorrect source line attributions
samples % linenr info image name
symbol name
2338141 61.0359 fast.cpp:56 libopencv_features2d.so.3.0.0
void cv::FAST_t<16>(cv::_InputArray const&, std::vector<cv::KeyPoint,
std::allocator<cv::KeyPoint> >&, int, bool)
761503 19.8786 fast_score.cpp:121 libopencv_features2d.so.3.0.0
int cv::cornerScore<16>(unsigned char const*, int const*, int)
346500 9.0452 (no location information) libz.so.1.2.8
/lib/x86_64-linux-gnu/libz.so.1.2.8
305026 7.9625 (no location information) libpng12.so.0.50.0
/lib/x86_64-linux-gnu/libpng12.so.0.50.0
$ opannotate -s -i "void cv::FAST_t<16>(cv::_InputArray const&,
std::vector<cv::KeyPoint, std::allocator<cv::KeyPoint> >&, int, bool)"
Doing the above I get the following output
$ opannotate -s -i "void cv::FAST_t<16>(cv::_InputArray const&,
std::vector<cv::KeyPoint, std::allocator<cv::KeyPoint> >&, int, bool)"
Using
/home/pmousoul/Downloads/opencv3/opencv/build/bin/oprofile_data/samples/
for session-dir
WARNING! Some of the events were throttled. Throttling occurs when
the initial sample rate is too high, causing an excessive number of
interrupts. Decrease the sampling frequency. Check the directory
/home/pmousoul/Downloads/opencv3/opencv/build/bin/oprofile_data/samples/current/stats/throttled
for the throttled event names.
/*
* Command line: opannotate -s -i void cv::FAST_t<16>(cv::_InputArray
const&, std::vector<cv::KeyPoint, std::allocator<cv::KeyPoint> >&, int,
bool)
*
* Interpretation of command line:
* Output annotated source file with samples
* Output all files
*
* CPU: Intel Ivy Bridge microarchitecture, speed 2700 MHz (estimated)
* Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a
unit mask of 0x00 (No unit mask) count 90000
*/
What I'm I doing wrong?
As for the ophelp duplicated output on ARM Cortex-A7 MPCore:
$ ophelp
oprofile: available events for CPU type "ARM Cortex-A7"
See Cortex-A7 MPCore Technical Reference Manual
Cortex A7 DDI (ARM DDI 0464D, revision r0p3)
For architectures using unit masks, you may be able to specify
unit masks by name. See 'operf' or 'ocount' man page for more details.
SW_INCR: (counter: 1, 2, 3, 4, 5, 6)
Software increment of PMNC registers (min count: 500)
L1I_CACHE_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 instruction cache refill (min count: 500)
L1I_TLB_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 instruction TLB refill (min count: 500)
L1D_CACHE_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data cache refill (min count: 500)
L1D_CACHE: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data cache access (min count: 500)
L1D_TLB_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data TLB refill (min count: 500)
LD_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Load instruction architecturally executed, condition code pass (min
count: 500)
ST_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Store instruction architecturally executed, condition code pass (min
count: 500)
INST_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Instruction architecturally executed (min count: 500)
EXC_TAKEN: (counter: 1, 2, 3, 4, 5, 6)
Exception taken (min count: 500)
EXC_RETURN: (counter: 1, 2, 3, 4, 5, 6)
Exception return instruction architecturally executed (min count: 500)
CID_WRITE_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Write to CONTEXTIDR register architecturally executed (min count: 500)
PC_WRITE_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Software change of the PC architecturally executed, condition code pass
(min count: 500)
BR_IMMED_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Immediate branch instruction architecturally executed (min count: 500)
BR_RETURN_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Procedure return instruction architecturally executed, condition code
pass (min count:
500)
UNALIGNED_LDST_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Unaligned load or store instruction architecturally executed, condition
code pass (min
count: 500)
BR_MIS_PRED: (counter: 1, 2, 3, 4, 5, 6)
Mispredicted or not predicted branch speculatively executed (min count:
500)
BR_PRED: (counter: 1, 2, 3, 4, 5, 6)
Predictable branch speculatively executed (min count: 500)
MEM_ACCESS: (counter: 1, 2, 3, 4, 5, 6)
Data memory access (min count: 500)
L1I_CACHE: (counter: 1, 2, 3, 4, 5, 6)
Level 1 instruction cache access (min count: 500)
L1D_CACHE_WB: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data cache write-back (min count: 500)
L2D_CACHE: (counter: 1, 2, 3, 4, 5, 6)
Level 2 data cache access (min count: 500)
L2D_CACHE_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 2 data cache refill (min count: 500)
L2D_CACHE_WB: (counter: 1, 2, 3, 4, 5, 6)
Level 2 data cache write-back (min count: 500)
BUS_ACCESS: (counter: 1, 2, 3, 4, 5, 6)
Bus access (min count: 500)
MEMORY_ERROR: (counter: 1, 2, 3, 4, 5, 6)
Local memory error (min count: 500)
INST_SPEC: (counter: 1, 2, 3, 4, 5, 6)
Instruction speculatively executed (min count: 500)
TTBR_WRITE_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Write to TTBR architecturally executed, condition code pass (min count:
500)
BUS_CYCLES: (counter: 1, 2, 3, 4, 5, 6)
Bus cycle (min count: 500)
CPU_CYCLES: (counter: 0)
CPU cycle (min count: 100000)
SW_INCR: (counter: 1, 2, 3, 4, 5, 6)
Software increment of PMNC registers (min count: 500)
L1I_CACHE_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 instruction cache refill (min count: 500)
L1I_TLB_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 instruction TLB refill (min count: 500)
L1D_CACHE_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data cache refill (min count: 500)
L1D_CACHE: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data cache access (min count: 500)
L1D_TLB_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data TLB refill (min count: 500)
LD_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Load instruction architecturally executed, condition code pass (min
count: 500)
ST_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Store instruction architecturally executed, condition code pass (min
count: 500)
INST_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Instruction architecturally executed (min count: 500)
EXC_TAKEN: (counter: 1, 2, 3, 4, 5, 6)
Exception taken (min count: 500)
EXC_RETURN: (counter: 1, 2, 3, 4, 5, 6)
Exception return instruction architecturally executed (min count: 500)
CID_WRITE_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Write to CONTEXTIDR register architecturally executed (min count: 500)
PC_WRITE_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Software change of the PC architecturally executed, condition code pass
(min count: 500)
BR_IMMED_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Immediate branch instruction architecturally executed (min count: 500)
BR_RETURN_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Procedure return instruction architecturally executed, condition code
pass (min count:
500)
UNALIGNED_LDST_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Unaligned load or store instruction architecturally executed, condition
code pass (min
count: 500)
BR_MIS_PRED: (counter: 1, 2, 3, 4, 5, 6)
Mispredicted or not predicted branch speculatively executed (min count:
500)
BR_PRED: (counter: 1, 2, 3, 4, 5, 6)
Predictable branch speculatively executed (min count: 500)
MEM_ACCESS: (counter: 1, 2, 3, 4, 5, 6)
Data memory access (min count: 500)
L1I_CACHE: (counter: 1, 2, 3, 4, 5, 6)
Level 1 instruction cache access (min count: 500)
L1D_CACHE_WB: (counter: 1, 2, 3, 4, 5, 6)
Level 1 data cache write-back (min count: 500)
L2D_CACHE: (counter: 1, 2, 3, 4, 5, 6)
Level 2 data cache access (min count: 500)
L2D_CACHE_REFILL: (counter: 1, 2, 3, 4, 5, 6)
Level 2 data cache refill (min count: 500)
L2D_CACHE_WB: (counter: 1, 2, 3, 4, 5, 6)
Level 2 data cache write-back (min count: 500)
BUS_ACCESS: (counter: 1, 2, 3, 4, 5, 6)
Bus access (min count: 500)
MEMORY_ERROR: (counter: 1, 2, 3, 4, 5, 6)
Local memory error (min count: 500)
INST_SPEC: (counter: 1, 2, 3, 4, 5, 6)
Instruction speculatively executed (min count: 500)
TTBR_WRITE_RETIRED: (counter: 1, 2, 3, 4, 5, 6)
Write to TTBR architecturally executed, condition code pass (min count:
500)
BUS_CYCLES: (counter: 1, 2, 3, 4, 5, 6)
Bus cycle (min count: 500)
CPU_CYCLES: (counter: 0)
CPU cycle (min count: 100000)
EXC_IRQ: (counter: 1, 2, 3, 4, 5, 6)
IRQ exception taken (min count: 500)
EXC_FIQ: (counter: 1, 2, 3, 4, 5, 6)
FIQ exception taken (min count: 500)
EXT_MEM_REQ: (counter: 1, 2, 3, 4, 5, 6)
External memory request (min count: 500)
EXT_MEM_REQ_NC: (counter: 1, 2, 3, 4, 5, 6)
Non-cacheable external memory request (min count: 500)
PREFETCH_LINEFILL: (counter: 1, 2, 3, 4, 5, 6)
Linefill because of prefetch (min count: 500)
PREFETCH_LINEFILL_DROP: (counter: 1, 2, 3, 4, 5, 6)
Prefetch linefill dropped (min count: 500)
READ_ALLOC_ENTER: (counter: 1, 2, 3, 4, 5, 6)
Entering read allocate mode (min count: 500)
READ_ALLOC: (counter: 1, 2, 3, 4, 5, 6)
Read allocate mode (min count: 500)
STALL_SB_FULL: (counter: 1, 2, 3, 4, 5, 6)
Data write operation that stalls the pipeline because the store buffer
is full (min count:
500)
BUS_ACCESS_LD: (counter: 1, 2, 3, 4, 5, 6)
Bus access, read (min count: 500)
BUS_ACCESS_ST: (counter: 1, 2, 3, 4, 5, 6)
Bus access, write (min count: 500)
LOCAL_CLUSTER_SNOOP: (counter: 1, 2, 3, 4, 5, 6)
Data read transaction snooped from another processor within the local
A7 cluster (min
count: 500)
There are a lot of duplicates on the above ophelp output - is this normal?
Thank you very much for you time,
cheers,
Panos
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