Re: [PATCH] Remove Powerpc OProfile events the kernel will reject

On 11/19/2015 11:54 AM, 大平怜 wrote:
> Carl, Will,
> 
> After this particular commit, I cannot run any OProfile command, even ophelp, on POWER8.
> 
> $ ./ophelp --version
> ./ophelp: oprofile 1.2.0git compiled on Nov 19 2015 10:43:15
> $ ./ophelp
> um rc_machine is not used
> um L1_latency is not used
> 
> The previous version on git (commit a58c3953a1c5f5fb00b873a5e22c878f9f4d5a2d) works fine.
> 
> Could you help fix this problem?

Hi,

It is surprising that commit 34715734fd6f4b44f32206541c8a2500514c9922 is causing things to fail.  That commit only changes 
events/ppc64/power8/events.  However, there seems to be some checks for unused unit masks.  The attached patch seems to address the issue. Could you give it ia try?  Carl does this patch look reasonable?

-Will

> 
> 
> Thanks,
> Rei Odaira
> 
> 
> 2015-11-18 10:34 GMT-06:00 Carl E. Love <[email protected] <mailto:[email protected]>>:
> 
> 
>     >
>     > The patch for eliminating the problem power 8 pmu events looks reasonable, so I committed it to the oprofile repository.  Thanks for the fix.
>     >
>     > When a proper pointer to the power8 pmu counter documentation becomes available there should be a patch to utils/ophelp.c.  It currently has the following in there, but search for "Power ISA 2.07" doesn't turn up anything on the www.power.org <http://www.power.org> website.
>     >
>     >       case CPU_PPC64_ARCH_V1:
>     >       case CPU_PPC64_POWER8:
>     >               event_doc =
>     >                       "This processor type is fully supported with operf.\n"
>     >                       "See Power ISA 2.07 at https://www.power.org/\n\n";
>     >               break;
>     Will:
> 
>     OK, still pushing for a good link.  So far, I just got a new link for
>     Power 7.  Still pushing for a link for Power 8.  It sounds like the
>     available Power 8 documentation is limited but there are plans for
>     updating it with more detail.  I will work on a patch when I get a link
>     for Power 8.
> 
>                    Carl Love
> 
> 
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diff --git a/events/ppc64/power8/unit_masks b/events/ppc64/power8/unit_masks
index 203af97..96b32c0 100644
--- a/events/ppc64/power8/unit_masks
+++ b/events/ppc64/power8/unit_masks
@@ -9,9 +9,26 @@
 #       to workaround oprofile's 32-bit limitation for event codes.
 #       See libpe_utils/op_pe_utils.cpp:_get_event_code for how these codes are
 #       used.
+#
+#note 1.   11/12/2015
+#
+# Some event requires the cache selector bits to be set to a non-zero
+# value in the processor performance counter setup register.  On Power 8, this
+# register is only writable by the hypervisor.  So the kernel must reject any
+# event where the lower three cache selector bits (bits 22:20) are not equal
+# to 0.  If/when an API is implemented to allow the kernel to request the
+# hypervisor write the register with the required value, these events can be
+# re-added to the list of supported events.  The issue is documented in the
+# powerpc kernel file arch/powerpc/perf/power8-pmu.c in function power8_get_constraint()
+# where the cache bits are ANDed with 0x7 if the unit is between 6 and 9.  If
+# cache bits are not zero, the function returns -1 to reject the event.
+#
+# The associated unit masks for these problem events are unused and also need
+# to be commented out.
+#
 name:zero type:mandatory default:0x0
 	0x0 No unit mask
-name:rc_machine type:mandatory default:0xde
-	0xde Thresholdable start/stop for rc machine for sampled instruction
-name:L1_latency type:mandatory default:0x67
-	0x67 Thresholdable start/stop for L1 sampled instruction load miss/reload
+## note 1 name:rc_machine type:mandatory default:0xde
+## note 1 	0xde Thresholdable start/stop for rc machine for sampled instruction
+## note 1 name:L1_latency type:mandatory default:0x67
+## note 1 	0x67 Thresholdable start/stop for L1 sampled instruction load miss/reload