[PATCH] Fix various i386 default unit masks (atom, nehalem, silvermont)

From 7ef98a784fa61b6b2556b5d9e896445e4fadff29 Mon Sep 17 00:00:00 2001
From: Saruman <Saruman@Rodrigo>
Date: Sat, 10 Dec 2016 12:05:36 +0100
Subject: [PATCH] Fix various i386 default unit masks (atom, nehalem,
 silvermont)

Some other non-unique unit masks were found in the i386 configuration.
This commit fixes them.
---
 events/i386/atom/unit_masks       | 2 +-
 events/i386/nehalem/unit_masks    | 2 +-
 events/i386/silvermont/unit_masks | 8 ++++----
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/events/i386/atom/unit_masks b/events/i386/atom/unit_masks
index 4802ddb..423e3e0 100644
--- a/events/i386/atom/unit_masks
+++ b/events/i386/atom/unit_masks
@@ -15,7 +15,7 @@ name:data_tlb_misses type:bitmask default:0x07
 	0x05 extra: dtlb_miss_ld DTLB misses due to load operations
 	0x09 extra: l0_dtlb_miss_ld L0_DTLB misses due to load operations
 	0x06 extra: dtlb_miss_st DTLB misses due to store operations
-name:page_walks type:bitmask default:0x03
+name:page_walks type:bitmask default:walks
 	0x03 extra: walks Number of page-walks executed
 	0x03 extra: cycles Duration of page-walks in core cycles
 name:x87_comp_ops_exe type:bitmask default:0x81
diff --git a/events/i386/nehalem/unit_masks b/events/i386/nehalem/unit_masks
index 8f60292..a5b6ab1 100644
--- a/events/i386/nehalem/unit_masks
+++ b/events/i386/nehalem/unit_masks
@@ -37,7 +37,7 @@ name:mem_inst_retired type:bitmask default:0x01
 	0x02 extra: stores Counts the number of instructions with an architecturally-visible store retired on the architected path
 name:mem_store_retired type:mandatory default:0x01
 	0x01 extra: dtlb_miss The event counts the number of retired stores that missed the DTLB
-name:uops_issued type:bitmask default:0x01
+name:uops_issued type:bitmask default:any
 	0x01 extra: any Counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i
 	0x01 extra: stalled_cycles Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i
 	0x02 extra: fused Counts the number of fused Uops that were issued from the Register Allocation Table to the Reservation Station
diff --git a/events/i386/silvermont/unit_masks b/events/i386/silvermont/unit_masks
index c0dac26..c478ab8 100644
--- a/events/i386/silvermont/unit_masks
+++ b/events/i386/silvermont/unit_masks
@@ -4,7 +4,7 @@
 # See http://ark.intel.com/ for help in identifying Silvermont based CPUs
 #
 include:i386/arch_perfmon
-name:rehabq type:exclusive default:0x1
+name:rehabq type:exclusive default:ld_block_st_forward
 	0x1 extra: ld_block_st_forward This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.
 	0x1 extra:pebs ld_block_st_forward_pebs This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.
 	0x2 extra: ld_block_std_notready This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time
@@ -28,7 +28,7 @@ name:mem_uops_retired type:exclusive default:0x1
 	0x20 extra:pebs hitm_pebs This event counts the number of load ops retired that got data from the other core or from the other module.
 	0x40 extra: all_loads This event counts the number of load ops retired
 	0x80 extra: all_stores This event counts the number of store ops retired
-name:page_walks type:exclusive default:0x1
+name:page_walks type:exclusive default:d_side_cycles
 	0x1 extra:edge d_side_walks This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.
 	0x1 extra: d_side_cycles This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.
 	0x2 extra:edge i_side_walks This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.
@@ -47,7 +47,7 @@ name:machine_clears type:exclusive default:0x8
 	0x1 extra: smc This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors.
 	0x2 extra: memory_ordering This event counts the number of times that pipeline was cleared due to memory ordering issues.
 	0x4 extra: fp_assist This event counts the number of times that pipeline stalled due to FP operations needing assists.
-name:br_inst_retired type:exclusive default:0x7e
+name:br_inst_retired type:exclusive default:jcc
 	0x7e extra: jcc JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.
 	0x7e extra:pebs jcc_pebs JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.
 	0xfe extra: taken_jcc TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.
@@ -64,7 +64,7 @@ name:br_inst_retired type:exclusive default:0x7e
 	0xeb extra:pebs non_return_ind_pebs NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.
 	0xbf extra: far_branch FAR counts the number of far branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.
 	0xbf extra:pebs far_branch_pebs FAR counts the number of far branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.
-name:br_misp_retired type:exclusive default:0x7e
+name:br_misp_retired type:exclusive default:jcc
 	0x7e extra: jcc JCC counts the number of mispredicted conditional branches (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.
 	0x7e extra:pebs jcc_pebs JCC counts the number of mispredicted conditional branches (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.
 	0xfe extra: taken_jcc TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.
-- 
2.1.4