Re: [PATCH] Fix various i386 default unit masks (atom, nehalem, silvermont)
William Cohen <[email protected]>
| Newsgroups | gmane.linux.oprofile |
|---|---|
| Message-ID | <[email protected]> |
On 01/10/2017 03:21 PM, Michael Petlan wrote: > On Mon, 9 Jan 2017, William Cohen wrote: >> On 01/09/2017 02:39 PM, Michael Petlan wrote: >> Hi Michael, >> >> Thanks for the updated version of the patch. The previous version of the patch was merged into the upstream and I attempted to put in a fix for the page walk, based on what was in other processors. Could you update the patch to apply to the upstream oprofile? > > Hi Will, > > The updated patch is attached. It fixes the remaining issue (Nehalem uops_issued). > >> >> Note that "cmask=%x" (a hex number afterZ) and then comman seperated list of other flags. Thus, the following isn't right: > > I see. Sorry for that mistake, I took the "cmask=edge" string from one of your > prior mails and didn't realize that "edge" is not a valid cmask. > > I hope, it's correct now. > > Thank you! > Michael Hi Michael, The patch looks fine and has been merged into the upstream oprofile git repository. -Will > >> >> --- a/events/i386/atom/unit_masks >> +++ b/events/i386/atom/unit_masks >> @@ -15,8 +15,8 @@ name:data_tlb_misses type:bitmask default:0x07 >> 0x05 extra: dtlb_miss_ld DTLB misses due to load operations >> 0x09 extra: l0_dtlb_miss_ld L0_DTLB misses due to load operations >> 0x06 extra: dtlb_miss_st DTLB misses due to store operations >> -name:page_walks type:bitmask default:0x03 >> - 0x03 extra: walks Number of page-walks executed >> +name:page_walks type:bitmask default:walks >> + 0x03 extra:cmask=edge walks Number of page-walks executed >> 0x03 extra: cycles Duration of page-walks in core cycles >> name:x87_comp_ops_exe type:bitmask default:0x81 >> 0x01 extra: s Floating point computational micro-ops executed >> >> -Will >> >>> >>> Michael >>> >>>> >>>> For the page_walks unit_mask there looks like there is a missing extra:cmask=edge for "Number of page-walks executed" otherwise the unit masks look identical. >>>> >>>> --- a/events/i386/atom/unit_masks >>>> +++ b/events/i386/atom/unit_masks >>>> @@ -15,7 +15,7 @@ name:data_tlb_misses type:bitmask default:0x07 >>>> 0x05 extra: dtlb_miss_ld DTLB misses due to load operations >>>> 0x09 extra: l0_dtlb_miss_ld L0_DTLB misses due to load operations >>>> 0x06 extra: dtlb_miss_st DTLB misses due to store operations >>>> -name:page_walks type:bitmask default:0x03 >>>> +name:page_walks type:bitmask default:walks >>>> 0x03 extra: walks Number of page-walks executed >>>> 0x03 extra: cycles Duration of page-walks in core cycles >>>> name:x87_comp_ops_exe type:bitmask default:0x81 >>>> >>>> >>>> The unit masks also look the same for any and stalled for nehalem. An extra: correction is needed here: >>>> >>>> --- a/events/i386/nehalem/unit_masks >>>> +++ b/events/i386/nehalem/unit_masks >>>> @@ -37,7 +37,7 @@ name:mem_inst_retired type:bitmask default:0x01 >>>> 0x02 extra: stores Counts the number of instructions with an architecturally-visible store retired on the architected path >>>> name:mem_store_retired type:mandatory default:0x01 >>>> 0x01 extra: dtlb_miss The event counts the number of retired stores that missed the DTLB >>>> -name:uops_issued type:bitmask default:0x01 >>>> +name:uops_issued type:bitmask default:any >>>> 0x01 extra: any Counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i >>>> 0x01 extra: stalled_cycles Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i >>>> 0x02 extra: fused Counts the number of fused Uops that were issued from the Register Allocation Table to the Reservation Station >>>> >>>> >>>> -Will >>>> >> >> > > > ------------------------------------------------------------------------------ > Developer Access Program for Intel Xeon Phi Processors > Access to Intel Xeon Phi processor-based developer platforms. > With one year of Intel Parallel Studio XE. > Training and support from Colfax. > Order your platform today. http://sdm.link/xeonphi > > > > _______________________________________________ > oprofile-list mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/oprofile-list > ------------------------------------------------------------------------------ Developer Access Program for Intel Xeon Phi Processors Access to Intel Xeon Phi processor-based developer platforms. With one year of Intel Parallel Studio XE. Training and support from Colfax. Order your platform today. http://sdm.link/xeonphi