Re: [PATCH] oprofile: Add support for Intel Xeon Phi (Knights Landing)

Michael Petlan <[email protected]>
Newsgroups gmane.linux.oprofile
Message-ID <alpine.LRH.2.20.1705210035340.8978@Diego>
On Wed, 17 May 2017, William Cohen wrote:
> On 05/16/2017 06:54 PM, Michael Petlan wrote:
> > Hi,
> > 
> > attached patch for Intel Xeon Phi (Knights Landing/Knights Mill) oprofile
> > support. 
> > 
> > The events/umasks configuration has been taken from Intel Xeon Phi Processor
> > Performance Monitoring Reference Manual, volume 2. All the events were tested
> > on a Knights Mill machine.
> > 
> > Cheers,
> > Michael
> > 
> 
> Hi Michael,
> 
> I am starting to look over the patch. 
> 
> Is there a matching patch for the oprofile testsuite available?

Hi William,

testsuite patch is attached. I have tested it with the patched oprofile
on a Knights Mill machine and all the tests passed.

Cheers,
Michael

> 
> -Will
>

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oprofile-tests-knights-landing.patch (text/plain, 2.4 KB)
commit a29d0c752516d81dbd19717728abb7c0bf24c3ee
Author: Michael Petlan <[email protected]>
Date:   Sun May 21 00:26:13 2017 +0200

    Added support for Intel Knights Landing/Knights Mill processors

diff --git a/testsuite/lib/op_events.exp b/testsuite/lib/op_events.exp
index ec804d2..873b8a4 100644
--- a/testsuite/lib/op_events.exp
+++ b/testsuite/lib/op_events.exp
@@ -234,6 +234,26 @@ set op_event_table(skylake)                         \
 	}                                           \
     }
 
+set op_event_table(knightslanding)                  \
+    {                                               \
+	{                                           \
+	     {0 INST_RETIRED      0 500000}         \
+	     {1 CPU_CLK_UNHALTED  0 500000}         \
+	}                                           \
+	{                                           \
+	     {0 LLC_MISSES        0x41 10000}       \
+	     {1 LLC_REFS          0x4f 10000}       \
+	}                                           \
+	{                                           \
+	     {0 br_inst_retired any 500000}         \
+	     {1 br_misp_retired any 50000}          \
+	}                                           \
+	{                                           \
+	     {0 icache accesses 2000003}            \
+	     {1 icache misses 2000003}              \
+	}                                           \
+    }
+
 set op_event_table(athlon)                          \
     {                                               \
 	{                                           \
@@ -816,6 +836,8 @@ proc select_cpu_events {cpu_name} {
 	Intel_Broadwell_microarchitecture {set type arch_perf}
 	i386/skylake {set type skylake}
 	Intel_Skylake_microarchitecture {set type skylake}
+	i386/knightslanding {set type knightslanding}
+	Intel_Knights_Landing {set type knightslanding}
     }
 
     verbose "cpu type is $type"
diff --git a/testsuite/lib/op_util.exp b/testsuite/lib/op_util.exp
index 2f3695a..7f0473d 100644
--- a/testsuite/lib/op_util.exp
+++ b/testsuite/lib/op_util.exp
@@ -137,7 +137,9 @@ proc op_intel_perf_arch {cpu_type} {
 	    78 {set cpu_type i386/skylake}
 	    79 {set cpu_type i386/broadwell}
 	    86 {set cpu_type i386/broadwell}
+	    87 {set cpu_type i386/knightslanding}
 	    94 {set cpu_type i386/skylake}
+	   133 {set cpu_type i386/knightslanding}
 	}
     }
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