Update powerpc / P9 event list (PM_ST_CMPL,PM_ST_FIN)

The entries for PM_ST_CMPL and PM_ST_FIN event numbers conflict between the
ppc64/architected_events_v1/events file and the power9/events file.

PM_ST_FIN event is (P9) associated with #0x20016, PM_ST_CMPL has the
#0x200f0 event number.
    
This was noticed in a P9 environment when ophelp was not returning the expected
event number for PM_ST_FIN.
    
After closer review, all but four entries in the 'architected' list are
redundant with respect to the P9 list.  So our inclusion of that list in our
P9 event list file is an error.
    
This patch
 - removes the include of architected_events from the p9 event list file.
 - adds CYCLES,PM_CYC,PM_RUN_CYC, PM_RUN_INST_CMPL to the p9 events file.


Signed-Off-By: Will Schmidt <[email protected]>
CC: Carl  



diff --git a/events/ppc64/power9/events b/events/ppc64/power9/events
index 2116c9b..5cbfed5 100644
--- a/events/ppc64/power9/events
+++ b/events/ppc64/power9/events
@@ -1,17 +1,18 @@
 
 #  Copyright OProfile authors
-#  Copyright (c) International Business Machines, 2017.
+#  Copyright (c) International Business Machines, 2017-2019.
 #  Contributed by Will Schmidt <[email protected]>.
 #
 #  IBM POWER9 Events
 
-include:ppc64/architected_events_v1
+# Disable the include here.  All of the events in 'architected_events_v1' are
+# represented in this (power9/events) event list.
+# include:ppc64/architected_events_v1
 
-# This table has been automatically generated with a preliminary list of
-# events, and is subject to verification and update.
-# Last Refresh. ( will schmidt , Jun 06,2017  ).
+# Initial ( will schmidt , Jun 06,2017  ).
+# Updated Apr 26, 2019.
 
 # Abbreviation hints:
 # BHS - Branch History Table
 # DARQ - Data and Address Recycle/Recirculation Queue
 # ERAT - Effective to Real Address Translation
@@ -27,10 +28,14 @@ include:ppc64/architected_events_v1
 # RIS - Random Instruction Sampling
 # rty - retry
 # TAGE - Tagged Geometric History Length predictor (branch prediction)
 # TM - Transactional Memory
 
+event:0x1e counters:0,1,2,3 um:zero minimum:100000 name:PM_CYC : Cycles .
+event:0x100f0 counters:0 um:zero minimum:100000 name:CYCLES : Cycles
+event:0x600f4 counters:5 um:zero minimum:100000 name:PM_RUN_CYC : Run_cycles.
+event:0x500fa counters:4 um:zero minimum:100000 name:PM_RUN_INST_CMPL : Run_Instructions.
 
 event:0x0000045050 counters:3       um:zero minimum:10000  name:PM_1FLOP_CMPL : one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed
 event:0x00000100F2 counters:0       um:zero minimum:10000  name:PM_1PLUS_PPC_CMPL : 1 or more ppc insts finished
 event:0x00000400F2 counters:3       um:zero minimum:10000  name:PM_1PLUS_PPC_DISP : Cycles at least one Instr Dispatched
 event:0x000004D052 counters:3       um:zero minimum:10000  name:PM_2FLOP_CMPL : DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg