ARM L2C-310 cache controller interconnect question

Hello,

I was reading about cache lockdown in ARM's L2C-310 (or PL310) cache
controller in [1]. Based on the documentation, it looks like the cache
lockdown by master (CPU) is implemented depending upon how the signal
AyUSERSx[7:5] is connected. It looks like it makes the most sense to
hook up this signal like in the example, "System including four
Cortex-A9 MPCore processors and L2C-310" so that the lockdown register
0 determines what cache ways are available for CPU0, lockdown register
1 determines what cache ways are available for CPU 1, etc.

The problem is that I cannot find out how AyUSERSx[7:5] is connected
in my system, and I cannot determine if cache lockdown by master is
supported (the documentation says that this is an optional feature). I
believe that these options are determined by the SoC manufacturers,
and are not available to the public. I am specifically curious about
how this is set up in the PandaBoard ES, which uses a TI OMAP4460, and
the ODROID-X, which uses a Samsung Exynos 4412. Do you know where I
can find this information out?

Thanks very much,
Chris Kenna

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246h/ch02s03s06.html