Re: Memory inconsistency when mmap()ping
"Christoph M." <[email protected]> Thu, 3 Jan 2013 15:13:04 +0100
| Newsgroups | gmane.linux.ports.arm.general |
|---|---|
| Message-ID | <CAHB2gtQGGFXG0c2NYv0fNqvfndhyvQnmLL=oHMXMOWNX9pCgZw@mail.gmail.com> |
On Wed, Jan 2, 2013 at 5:13 PM, Russell King - ARM Linux <[email protected]> wrote: > On Wed, Jan 02, 2013 at 12:38:47PM +0100, Christoph M. wrote: >> On Wed, Jan 2, 2013 at 11:21 AM, Russell King - ARM Linux >> <[email protected]> wrote: >> > On Wed, Jan 02, 2013 at 10:59:55AM +0100, Christoph M. wrote: >> >> I'm experiencing a strange problem when mmap()ping memory >> >> to userspace on ARM-based Linux System. >> > >> > You're running into the standard problems with virtually tagged caches. >> >> On bootup the kernel reports this: >> [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction c >> ache >> >> So the cache should be physically tagged and I would expect that there are >> no aliasing problems. >> >> >> Now to the technical details: >> >> * The memory is allocated using kzalloc(PAGE_SIZE, GFP_KERNEL); >> >> * The event counter is a u32 value which is stored at offset 0 of >> >> the buffer. >> >> * When accessing (read/write) the buffer from kernelspace a call >> >> to mb() is done afterwards. >> >> * My mmap() code does this: >> >> vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); >> > >> > And doing that will violate the requirements of the ARMv7 architecture >> > that all mappings of the same physical memory space will be of the same >> > type (let alone, have the same attributes.) >> >> Is such a mapping possible for sharing a physical page between >> userspace and kernelspace? >> If yes, how is such a mapping, using the same attributes, done? > > Don't use pgprot_noncached() - you'll then have the same memory type > and cacheability as the kernel mapping and everything should work on > PIPT and non-aliasing VIPT caches. Just successfully tested my driver without pgprot_noncached(). Works fine on both of my testmachines (i.MX53, i.MX6 Quad). > It _won't_ work on VIVT or aliasing VIPT caches though. FWIW: For the ARMv7 architecture all data and unified caches behave as Physically Indexed Physically Tagged (PIPT) caches. This means they are either PIPT or non-aliasing VIPT caches. Thank you very much for your help! BR Christoph