Re: Query regarding Linux Arm pagetable setup
Dushyant Behl <[email protected]> Sat, 7 May 2016 01:31:27 +0530
| Newsgroups | gmane.linux.ports.arm.general |
|---|---|
| Message-ID | <CAHF350KE3NUp1idYS4Zmp=RyOdKex=2AYvWrTzO=Usht29LUHw@mail.gmail.com> |
On Thu, May 5, 2016 at 10:24 PM, Catalin Marinas <[email protected]> wrote: > On Thu, May 05, 2016 at 04:17:08PM +0530, Dushyant Behl wrote: >> Can someone explain how the kernel is using both the TTBR0 and TTBR1 >> and how some mappings which should've been present in TTBR1 are >> actually used through the TTBR0 register? > > With the 3-1 split, TTBR1 only needs to cover 1GB of virtual memory. > This means that Level 1 page table is disabled (pgd/pud) and the first 3 > pmd pages are also skipped. The architecture does not allow TTBRx sizes > with a single entry at the top level, meaning that the number of levels > must be reduced. Aah, this is the reason why the table looked strange to me. Thanks. -- Dushyant