Re: [PATCH v9 01/12] dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
Krzysztof Kozlowski <[email protected]>
| Newsgroups | gmane.linux.kernel.clk,gmane.linux.drivers.devicetree,gmane.linux.kernel,gmane.linux.ports.arm.kernel |
|---|---|
| Message-ID | <20260804-tough-reindeer-of-zoology-6ccd59@quoll> |
On Sun, Aug 02, 2026 at 11:33:33PM +0300, Stefan Dösinger wrote: > These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. > Clocks go from oscillator -> top -> matrix -> LSP, with a register in > top controlling most clocks that get passed to matrix and a register in > matrix controlling all the clocks that get passed to LSP. > > Generally every device has two clocks (one work clock, and one that > connects it to the bus, I call it PCLK), two reset bits (I don't know > what the difference is - sometimes asserting one is enough to reset the > device, sometimes both need to be asserted). PCLK and WCLK are > controlled by individual gates. Some devices have a mux and/or a > divider for their work clock. Some devices, like the GPIO controller, > only have reset bits and no clocks. > > The top clock controller is fed by a 26 MHz external oscillator and has 4 > PLLs to generate other clock rates. ZTE's kernel mostly relies on the > boot ROM to set up PLLs, but one LTE-related PLL is not configured > on some boards. Therefore my driver contains code to program PLLs. It > produces identical settings as the boot ROM for the pre-programmed > frequencies. > > Not all clocks will have an explicit user in the end. I am defining a > lot of them simply to shut them off. The boot loader sets up a few of > the proprietary timers, which will send regular IRQs (although the > kernel of course doesn't need to listen to them). I don't plan to add a > driver for the proprietary timer as I see no use for them - the ARM arch > timer works just fine. I will add a driver for the very similar > proprietary watchdog though. > > The clock list in this patch is pretty complete but not exhaustive. > There are other bits that are enabled, but I couldn't deduce what they > are controlling by trial and error. Some of them seem to do nothing. > Others cause an instant hang of the board when disabled. It is quite > likely that a handful more clocks will be added in the future, but not a > large number. > > Signed-off-by: Stefan Dösinger <[email protected]> > > --- > > Changes v8->v9: Reviewed-by: Krzysztof Kozlowski <[email protected]> Best regards, Krzysztof