Re: [PATCH] arm64: dts: rockchip: Enable the NPU on LubanCat 4

On Tue, Aug 4, 2026 at 9:49 AM Pufan Jin <[email protected]> wrote:
>
> The three RKNN cores and their IOMMUs are disabled by default in the SoC
> dtsi, so the board has to describe the NPU supply before they can be
> enabled.
>
> This board feeds both the NPU logic and its SRAM from a single RK8602
> output on i2c1. The vendor DTS makes that explicit by giving the same
> regulator node two labels, vdd_npu_s0 and vdd_npu_mem_s0, and then
> handing one to rknpu-supply and the other to mem-supply. There is no
> separate memory rail to describe, so npu-supply and sram-supply both
> point at vdd_npu_s0. The binding requires both properties.
>
> Neither property is what actually enables the rail: the rocket driver
> never requests a regulator, it only takes clocks, resets, register
> ranges and a power domain. The rk3588 power domain driver marks
> RK3588_PD_NPU as needing a regulator, so the rail has to be described on
> pd_npu, the root of VD_NPU that the three per-core domains hang off.
> This matches what rock-5b does.
As you mentioned here, the power domain will control the regulator. So
please remove the regulator-always-on from the regulator.

Jimmy