[PATCH v2 7/9] ARM: dts: stm32: add STM32H7R7 SoC

Describe the Cortex-M7 CPU, clocks, TIM5 clockevent, UART4, SDMMC1,
EXTI, system configuration controller and GPIO banks available on
STM32H7R7 devices. Expose the RCC reset controller for peripheral
consumers.

Signed-off-by: Liu Changjie <[email protected]>
---
Changes in v2:
- Clock TIM5 from a DT fixed-clock instead of the RCC provider, since the
  timer is initialized via TIMER_OF_DECLARE() before the RCC platform driver;
  the rate is guaranteed by the first-stage firmware.
- Use a single "st,stm32h7rs-rcc" compatible for the RCC node.
- Switch the GPIO bank unit-addresses to the pinctrl "ranges" offsets
  (gpio@0, gpio@400 ... gpio@3c00) to fix the dtc unit-address/reg
  warnings reported by the kernel test robot.

 arch/arm/boot/dts/st/stm32h7r7.dtsi | 261 ++++++++++++++++++++++++++++
 1 file changed, 261 insertions(+)
 create mode 100644 arch/arm/boot/dts/st/stm32h7r7.dtsi

diff --git a/arch/arm/boot/dts/st/stm32h7r7.dtsi b/arch/arm/boot/dts/st/stm32h7r7.dtsi
new file mode 100644
index 000000000..4e29dc2dd
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32h7r7.dtsi
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include "../armv7-m.dtsi"
+#include <dt-bindings/clock/stm32h7rs-clks.h>
+#include <dt-bindings/mfd/stm32h7rs-rcc.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-m7";
+			device_type = "cpu";
+			reg = <0>;
+			clocks = <&rcc STM32H7RS_SYS_CK>;
+		};
+	};
+
+	clocks {
+		clk_hse: clock-hse {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		clk_lse: clock-lse {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+
+		clk_tim5: clock-tim5 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <250000000>;
+		};
+	};
+
+	soc {
+		timer5: timer@40000c00 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000c00 0x400>;
+			interrupts = <54>;
+			clocks = <&clk_tim5>;
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <85>;
+			clocks = <&rcc STM32H7RS_UART4_CK>;
+			status = "disabled";
+		};
+
+		sdmmc1: mmc@52007000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x",
+				     "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x52007000 0x1000>;
+			interrupts = <108>;
+			clocks = <&rcc STM32H7RS_SDMMC1_CK>;
+			clock-names = "apb_pclk";
+			resets = <&rcc STM32H7RS_AHB5_RESET(SDMMC1)>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
+			status = "disabled";
+		};
+
+		exti: interrupt-controller@58000000 {
+			compatible = "st,stm32h7-exti";
+			reg = <0x58000000 0x400>;
+			interrupts = <16>, <17>, <18>, <19>,
+				     <20>, <21>, <22>, <23>,
+				     <24>, <25>, <26>, <27>,
+				     <28>, <29>, <30>, <31>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		syscfg: syscon@58000400 {
+			compatible = "st,stm32-syscfg", "syscon";
+			reg = <0x58000400 0x400>;
+		};
+
+		pinctrl: pinctrl@58020000 {
+			compatible = "st,stm32h7rs-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x58020000 0x4000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x130>;
+
+			gpioa: gpio@0 {
+				reg = <0x0 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOA_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 0 16>;
+				st,bank-name = "GPIOA";
+			};
+
+			gpiob: gpio@400 {
+				reg = <0x400 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOB_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 16 16>;
+				st,bank-name = "GPIOB";
+			};
+
+			gpioc: gpio@800 {
+				reg = <0x800 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOC_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 32 16>;
+				st,bank-name = "GPIOC";
+			};
+
+			gpiod: gpio@c00 {
+				reg = <0xc00 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOD_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 48 16>;
+				st,bank-name = "GPIOD";
+			};
+
+			gpioe: gpio@1000 {
+				reg = <0x1000 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOE_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 64 16>;
+				st,bank-name = "GPIOE";
+			};
+
+			gpiof: gpio@1400 {
+				reg = <0x1400 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOF_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 80 16>;
+				st,bank-name = "GPIOF";
+			};
+
+			gpiog: gpio@1800 {
+				reg = <0x1800 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOG_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 96 16>;
+				st,bank-name = "GPIOG";
+			};
+
+			gpioh: gpio@1c00 {
+				reg = <0x1c00 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOH_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 112 16>;
+				st,bank-name = "GPIOH";
+			};
+
+			gpiom: gpio@3000 {
+				reg = <0x3000 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOM_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 192 16>;
+				st,bank-name = "GPIOM";
+			};
+
+			gpion: gpio@3400 {
+				reg = <0x3400 0x400>;
+				clocks = <&rcc STM32H7RS_GPION_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 208 16>;
+				st,bank-name = "GPION";
+			};
+
+			gpioo: gpio@3800 {
+				reg = <0x3800 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOO_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 224 16>;
+				st,bank-name = "GPIOO";
+			};
+
+			gpiop: gpio@3c00 {
+				reg = <0x3c00 0x400>;
+				clocks = <&rcc STM32H7RS_GPIOP_CK>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 240 16>;
+				st,bank-name = "GPIOP";
+			};
+		};
+
+		rcc: reset-clock-controller@58024400 {
+			compatible = "st,stm32h7rs-rcc";
+			reg = <0x58024400 0x400>;
+			clocks = <&clk_hse>, <&clk_lse>;
+			clock-names = "hse", "lse";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
+
+&systick {
+	clock-frequency = <250000000>;
+	status = "okay";
+};
-- 
2.55.0