Re: Fixing MIPS delay slot emulation weakness?

Hi,

On Mon, Dec 17, 2018 at 01:55:28AM +0000, Maciej W. Rozycki wrote:
>  As to actual implementations I believe all the Cavium Octeon line CPUs 
> (David, please correct me if I am wrong) have no FPU and they have vendor 
> extensions beyond the base ISA + ASE instruction set.  Arguably you could 
> say that their additional instructions should not be scheduled into FPU 
> branch delay slots then, however the toolchain will happily do that, as I 
> wrote before.

Octeon III added/introduced FPU.

A.