Patch "mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS" has been added to the 4.14-stable tree

This is a note to let you know that I've just added the patch titled

    mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS

to the 4.14-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     mm-zsmalloc-prepare-to-variable-max_physmem_bits.patch
and it can be found in the queue-4.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.


From foo@baz Thu Nov  4 09:33:05 AM CET 2021
From: Florian Fainelli <[email protected]>
Date: Wed,  3 Nov 2021 13:57:03 -0700
Subject: mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS
To: [email protected]
Cc: [email protected], Greg Kroah-Hartman <[email protected]>, Sasha Levin <[email protected]>, "Kirill A. Shutemov" <[email protected]>, Nitin Gupta <[email protected]>, Minchan Kim <[email protected]>, Andy Lutomirski <[email protected]>, Borislav Petkov <[email protected]>, Linus Torvalds <[email protected]>, Peter Zijlstra <[email protected]>, Sergey Senozhatsky <[email protected]>, Thomas Gleixner <[email protected]>, [email protected], Ingo Molnar <[email protected]>, Florian Fainelli <[email protected]>, Vineet Gupta <[email protected]>, Russell King <[email protected]>, Ralf Baechle <[email protected]>, Benjamin Herrenschmidt <[email protected]>, Paul Mackerras <[email protected]>, Michael Ellerman <mpe@ellerm
 an.id.au>, Ingo Molnar <[email protected]>, "H. Peter Anvin" <[email protected]>, [email protected] (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Arnd Bergmann <[email protected]>, Stefan Agner <stefan@agn
 er.ch>, Thomas Bogendoerfer <[email protected]>, Mike Rapoport <[email protected]>, [email protected] (open list:SYNOPSYS ARC ARCHITECTURE), [email protected] (moderated list:ARM PORT), [email protected] (open list:MIPS), [email protected] (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), [email protected] (open list:GENERIC INCLUDE/ASM HEADER FILES)
Message-ID: <[email protected]>

From: "Kirill A. Shutemov" <[email protected]>

commit 02390b87a9459937cdb299e6b34ff33992512ec7 upstream

With boot-time switching between paging mode we will have variable
MAX_PHYSMEM_BITS.

Let's use the maximum variable possible for CONFIG_X86_5LEVEL=y
configuration to define zsmalloc data structures.

The patch introduces MAX_POSSIBLE_PHYSMEM_BITS to cover such case.
It also suits well to handle PAE special case.

Signed-off-by: Kirill A. Shutemov <[email protected]>
Reviewed-by: Nitin Gupta <[email protected]>
Acked-by: Minchan Kim <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Sergey Senozhatsky <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
 arch/x86/include/asm/pgtable-3level_types.h |    1 +
 arch/x86/include/asm/pgtable_64_types.h     |    2 ++
 mm/zsmalloc.c                               |   13 +++++++------
 3 files changed, 10 insertions(+), 6 deletions(-)

--- a/arch/x86/include/asm/pgtable-3level_types.h
+++ b/arch/x86/include/asm/pgtable-3level_types.h
@@ -44,5 +44,6 @@ typedef union {
  */
 #define PTRS_PER_PTE	512
 
+#define MAX_POSSIBLE_PHYSMEM_BITS	36
 
 #endif /* _ASM_X86_PGTABLE_3LEVEL_DEFS_H */
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -40,6 +40,8 @@ typedef struct { pteval_t pte; } pte_t;
 #define P4D_SIZE	(_AC(1, UL) << P4D_SHIFT)
 #define P4D_MASK	(~(P4D_SIZE - 1))
 
+#define MAX_POSSIBLE_PHYSMEM_BITS	52
+
 #else /* CONFIG_X86_5LEVEL */
 
 /*
--- a/mm/zsmalloc.c
+++ b/mm/zsmalloc.c
@@ -83,18 +83,19 @@
  * This is made more complicated by various memory models and PAE.
  */
 
-#ifndef MAX_PHYSMEM_BITS
-#ifdef CONFIG_HIGHMEM64G
-#define MAX_PHYSMEM_BITS 36
-#else /* !CONFIG_HIGHMEM64G */
+#ifndef MAX_POSSIBLE_PHYSMEM_BITS
+#ifdef MAX_PHYSMEM_BITS
+#define MAX_POSSIBLE_PHYSMEM_BITS MAX_PHYSMEM_BITS
+#else
 /*
  * If this definition of MAX_PHYSMEM_BITS is used, OBJ_INDEX_BITS will just
  * be PAGE_SHIFT
  */
-#define MAX_PHYSMEM_BITS BITS_PER_LONG
+#define MAX_POSSIBLE_PHYSMEM_BITS BITS_PER_LONG
 #endif
 #endif
-#define _PFN_BITS		(MAX_PHYSMEM_BITS - PAGE_SHIFT)
+
+#define _PFN_BITS		(MAX_POSSIBLE_PHYSMEM_BITS - PAGE_SHIFT)
 
 /*
  * Memory for allocating for handle keeps object position by


Patches currently in stable-queue which might be from [email protected] are

queue-4.14/mm-zsmalloc-prepare-to-variable-max_physmem_bits.patch
queue-4.14/arch-pgtable-define-max_possible_physmem_bits-where-needed.patch