[PATCH] powerpc/traps: Recover from L1 instruction cache parity errors on e500v2

There is no attempt to recover from an L1 instruction cache parity
error on e500v2 platforms. When this kind of error happens, we fall in
the die_mce() while we could recover from it (cf §3.1 in [1])

Implement a similar recovery than the one implemented on the e500mc
platforms. It consists of invalidating the entire L1 instruction cache
when parity errors are detected.

[1]: https://www.nxp.jp/docs/en/application-note/AN3532.pdf

Signed-off-by: Bastien Curutchet <[email protected]>
---
Hi all,

There is a real use case behind this: the device I'm working on is a
space product. It encounters this kind of parity errors when it gets
hit by radiations.

To test it, I made a module that triggers the parity errors by a
register of the P2020 that allows to corrupt the cache, you can find
this module here:
https://github.com/bastien-curutchet/linux/tree/b4/icache-parity-error
---
 arch/powerpc/kernel/traps.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 629f2a2d4780..f8a4019153a0 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -724,8 +724,21 @@ int machine_check_e500(struct pt_regs *regs)
 
 	if (reason & MCSR_MCP)
 		pr_cont("Machine Check Signal\n");
-	if (reason & MCSR_ICPERR)
+	if (reason & MCSR_ICPERR) {
 		pr_cont("Instruction Cache Parity Error\n");
+
+		/*
+		 * This is recoverable by invalidating the I-Cache.
+		 * The I-cache flash invalidate clears all lines;
+		 * correct instructions will be re-fetched from memory.
+		 */
+		mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
+		while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
+			;
+
+		return 1;
+	}
+
 	if (reason & MCSR_DCP_PERR)
 		pr_cont("Data Cache Push Parity Error\n");
 	if (reason & MCSR_DCPERR)

---
base-commit: 0fed5eb44e49e79d824edc4ccce012bb57994300
change-id: 20260831-icache-parity-error-b8c6b1ca0a64

Best regards,
-- 
Bastien Curutchet <[email protected]>