Re: [PATCH v2 3/3] sh: dma: Correct the number of DMA channels in SH7709
John Paul Adrian Glaubitz <[email protected]>
| Newsgroups | gmane.linux.ports.sh.devel,gmane.linux.kernel |
|---|---|
| Message-ID | <8205bc2cb9f983914ff6920deed3f54893713ba0.camel@physik.fu-berlin.de> |
Hi Geert! On Thu, 2023-06-08 at 11:58 +0200, Geert Uytterhoeven wrote: > > > > Aren't we dropping SH_DMAC_BASE1 in the other patch anyway? > > Only for the SH4 parts that do not have it. > It is still set in arch/sh/include/cpu-sh4a/cpu/dma.h for the SH4a parts with > 12 channels and 2 DMACs. OK, thanks for the clarification. I will review the other patches tonight. > > > That is actually safer, as the user can override NR_ONCHIP_DMA_CHANNELS > > > when configuring his kernel, thus breaking DMA due to an incorrect > > > value of SH_DMAC_NR_MD_CH. > > > > > > Unfortunately we cannot protect against that when using a single DMAC, > > > as SH_DMAC_NR_MD_CH can be either 4, 6, or 8. > > > > > > Perhaps this configuration should be moved from Kconfig to <cpu/dma.h>, > > > to protect against a user overriding this value? > > > > Isn't SH_DMAC_NR_MD_CH already hardwired to the SoC being used? > > It depends on CONFIG_NR_ONCHIP_DMA_CHANNELS, while it > should be fixed based on the SoC. I agree. However, I would be fine with merging this patch set first and fixing this particular issue in a follow-up series. Adrian -- .''`. John Paul Adrian Glaubitz : :' : Debian Developer `. `' Physicist `- GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913