[RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document.

Signed-off-by: Yoshinori Sato <[email protected]>
---
 .../bindings/clock/renesas,sh7750-cpg.yaml    | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml

diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index 000000000000..bf10a09440ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750 / SH7751 Clock Pulse Generator (CPG)
+
+maintainers:
+  - Yoshinori Sato <[email protected]>
+
+description:
+  The Clock Pulse Generator (CPG) generates core clocks for the SoC.  It
+  includes PLLs, and fixed and variable ratio dividers.
+
+  The CPG may also provide a Clock Domain for SoC devices,
+
+properties:
+  compatible:
+      - const: renesas,sh7750-cpg	# SH7750 / 7750S / 7751
+      - items:
+          - const: renesas,sh7750r-cpg	# SH7750R / 7751R
+
+  reg:
+    maxItems: 2
+    items:
+      - description: FRQCR register
+      - description: WDT registers
+
+  clocks: true
+
+  '#clock-cells':
+    const: 1
+
+  renesas,mode:
+    description: Board-specific settings of the MD0 - MD2 bits
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 6
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a7740-clock.h>
+        cpg: cpg@ffc00000 {
+		#clock-cells = <1>;
+	        compatible = "renesas,sh7750r-cpg","renesas,sh7750-cpg";
+    		clocks = <&xtal>;
+		reg = <0xffc00000 2>, <0xffc00008 4>;
+		renesas,mode = <0x05>
+        };
-- 
2.39.2