Re: [PATCH] sh: cache: Fill in invalidate_icache_all()
Geert Uytterhoeven <[email protected]>
| Newsgroups | gmane.comp.boot-loaders.u-boot,gmane.linux.ports.sh.devel |
|---|---|
| Message-ID | <CAMuHMdVvHtVmH+YP=m20U9-buXKi1+Kwcrkf8vWhQYagcg4JRQ@mail.gmail.com> |
Hi Marek, On Tue, Sep 10, 2024 at 7:55 PM Marek Vasut <[email protected]> wrote: > On 9/10/24 7:21 PM, Tom Rini wrote: > > On Tue, Sep 10, 2024 at 02:15:58AM +0200, Marek Vasut wrote: > > > >> Implement invalidate_icache_all() by clearing all V bits in > >> IC and OC. This is done by setting CCR cache control register > >> ICI and OCI bits. > >> > >> Signed-off-by: Marek Vasut <[email protected]> > >> --- > >> Cc: Ilias Apalodimas <[email protected]> > >> Cc: Nobuhiro Iwamatsu <[email protected]> > >> Cc: Tom Rini <[email protected]> > >> Cc: [email protected] > >> --- > >> arch/sh/cpu/sh4/cache.c | 11 +++++++---- > >> 1 file changed, 7 insertions(+), 4 deletions(-) > >> > >> diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c > >> index d3c480e79ed..99acc599965 100644 > >> --- a/arch/sh/cpu/sh4/cache.c > >> +++ b/arch/sh/cpu/sh4/cache.c > >> @@ -33,8 +33,9 @@ static inline void cache_wback_all(void) > >> } > >> } > >> > >> -#define CACHE_ENABLE 0 > >> -#define CACHE_DISABLE 1 > >> +#define CACHE_ENABLE 0 > >> +#define CACHE_DISABLE 1 > >> +#define CACHE_INVALIDATE 2 > >> > >> static int cache_control(unsigned int cmd) > >> { > >> @@ -46,7 +47,9 @@ static int cache_control(unsigned int cmd) > >> if (ccr & CCR_CACHE_ENABLE) > >> cache_wback_all(); > >> > >> - if (cmd == CACHE_DISABLE) > >> + if (cmd == CACHE_INVALIDATE) > >> + outl(CCR_CACHE_ICI | ccr, CCR); > >> + else if (cmd == CACHE_DISABLE) > >> outl(CCR_CACHE_STOP, CCR); > >> else > >> outl(CCR_CACHE_INIT, CCR); > >> @@ -103,7 +106,7 @@ void icache_disable(void) > >> > >> void invalidate_icache_all(void) > >> { > >> - puts("No arch specific invalidate_icache_all available!\n"); > >> + cache_control(CACHE_INVALIDATE); > >> } > >> > >> int icache_status(void) > > > > Thanks for filling this in, I wasn't sure how the implementation would > > look from a quick skim of the linux kernel code. > I believe it should look like the above, but lemme CC Geert to be on the > safe side. I have no idea. I removed the corresponding (but incomplete) code from Linux in commit 25c7d77d695a4104 ("sh: boot: Remove sh5 cache handling"), as it was a relic of sh5 cache handling. SH4 cache handling seems to be buried deeper. At least the above matches for invalidation: arch/sh/mm/cache-sh4.c- /* Flush I-cache */ arch/sh/mm/cache-sh4.c: ccr = __raw_readl(SH_CCR); arch/sh/mm/cache-sh4.c- ccr |= CCR_CACHE_ICI; arch/sh/mm/cache-sh4.c: __raw_writel(ccr, SH_CCR); Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds