Re: RTLinux Makefile for multiple sources

our makefiles are:

export-objs             := target-name.o

SRC = main.c file1.c file2.c
OBJS = main.o file1.o file2.o
TARGET = target-name.o

all: .depend $(TARGET)

$(TARGET):      $(OBJS)
        $(LD) -r -o $@ $^

include /usr/rtlinux/rtl.mk

CFLAGS += -I../includes
clean:
        rm -f *.o *~

depend .depend dep:
        $(CC) $(CFLAGS) -M $(SRC) > .depend


ifeq (.depend,$(wildcard .depend))
include .depend
endif

include $(RTL_DIR)/Rules.make


On Wednesday 26 January 2005 11:06, Allan Barredo wrote:
> Hi,
>
> Does someone have a simple makefile for compiling and linking an
> RTLinux application involving multiple source files? I have been
> trying in vain to create a simple application (file1.c) that calls
> some functions in another file (file2.c).
>
> My makefile looks like:
>
> #start of makefile
> include /usr/src/rtlinux/rtl.mk
>
> LDFLAGS += -lm
> TARGET := main.o
>
> LIBRARY_OBJS := file1.o file2.o
>
> LDFLAGS_$(TARGET) := $(LIBRARY_OBJS)
>
> $(TARGET): $(LIBRARY_OBJS)
>
> all: $(TARGET)
>
> %.o: %.o
>
> clean:
>
> include /usr/src/rtlinux/Rules.make
> #end of makefile
>
> The system complains about unresolved symbols (functions in file2.c)
> whenever I try to load main.o
>
> Please help. Thank you very much.
> _______________________________________________
> Rtl mailing list
> [email protected]
> http://www2.fsmlabs.com/mailman/listinfo/rtl

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