Re: Orphaning yosys/nextpnr & related packages

Hi folks,

I have taken over the maintenance of these tools, (except nextpnr,) having
previously picked up arachne-pnr around a year ago. Any assistance would,
of course, be appreciated; please reach out with improvements and fixes.

It's been nearly a decade since I properly used digital logic design tools,
but I have some experience in the space and previously worked on packaging
these in Homebrew. Hopefully that is enough to keep these usable in Fedora.

Best,
Alexander F. Lent <[email protected]>


On Mon, Jul 20, 2026 at 11:22 AM Gabriel L. Somlo <[email protected]> wrote:

> I'm no longer able to properly look after these packages, and having not
> heard back from any of my co-maintainers over the last week or so, I'm
> formally orphaning them in hope that they get picked up by someone who
> can do them justice.
>
> The list includes:
>
>         - yosys: HDL compilation, synthesis, and logic optimization
>                 - recent upstream support for SystemVerilog frontend may
>                   need to be packaged as standalone RPM, to be used by
>                   yosys as a buildrequires dependency
>         - yosyshq-abc (fork of Berkeley ABC logic optimizer and
>           tech-mapping tool, used by yosys as a dependency, but also
>           able to be used as a stand-alone tool)
>         - nextpnr: place-and-route tool for Lattice FPGAs
>                 - upstream has done extensive work on supporting other
>                   FPGA models, with various degrees of RPM
>                   packageability, and it would be nice to incorporate
>                   some of that in the Fedora version
>                 - **NOTE**: I can't *formally* orphan this package as my
>                   co-maintainer is the official owner, but walking
>                   away from it nonetheless !!!
>         - trellis: Lattice ECP5 FPGA dependency for nextpnr
>         - icestorm: Lattice iCE40 FPGA dependency for nextpnr
>         - python-migen: a "pythonic" HDL meta-language that elaborates
>           to Verilog before being compiled (e.g., with Yosys)
>
> Best,
> --Gabriel
> --
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