Page Protection , rings 0-4, and Supervisor/User mode

Hello,

I have a little question regarding Page Protection mechanism in IA-64.

The question deals with processor architecture:

  As I know , in IA-32 there is the known division into 4 rings:
ring 0 - for the kernel /Operating System
ring 1,2 - usually unused (in the past was used only by OS/2 if I am not 
wrong; and now used in Xen)
ring 3 - applications.

according to IA32 Manual (vol 3 , System Programming Guide)

"If the processor is currently operating at a CPL of 0, 1, or 2, it is in 
supervisor mode; if it is operating at a CPL of
3, it is in user mode. When the processor is in supervisor mode, it can 
access all pages; when in
user mode, it can access only user-level pages."

(let's ignore the WP flag for now).

Now:
I had tried to see if in IA-64 we have the same structure of four rings,and 
the same supervisor mode/user mode.

I had looked at Intel Itanium Architecture Software Developer Manual.
(Vol 2: System Architecture).

There is no occurrence for the phrase "supervisor mode".

I saw that there is something which is called "protection keys" but I do not 
know if it is relevant.

There is a paragraph in this manual titled "Privilege levels" which says 
there are 4 privilege levels (0-3)
but it talks about instructions and registers permissions and not about 
memory.

My question is :
In the aspect of access to  pages in rings 0-3, is IA-64 the same as IA-32 ?

I mean : do we have access to all pages when operating  in  ring 0-2 and 
when operating in ring 3 we can access only user-level pages?

Any idea? (a pointer to any info about this will be helpful)

Regards,
Sting

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