Re: Perfmon on Itanium

This list is for discussing Red Hat Linux on IA-64.  Detailed hardware
questions are probably better sent to the USENET comp.arch newsgroup.

If you really want to know how a particular Itanium processor does this,
you'd have to consult Intel or Intel documentation.  I don't know if Intel
publishes any info of this detail on the microarchitecture, but some useful
info might be gleaned from the documentation available for people writing
software.  Intel documentation is available at:
        http://developer.intel.com/design/itanium/index.htm

>1. Have the operation executed, but not allow the results to update
>the target register.

This is the usual way to implement this.  The register file write is the
latest point in the pipeline where the operation can be nullified, and thus
doing it here results in the least amount of pipeline stalls.  This does mean
that a function unit is wasted, but the performance loss from wasting a
function unit is usually much less than the performance loss of stalling
until the true/false condition can be determined.

Note that nullifying a predicated instruction is not much different from
nullifying an instruction in an annulled brach delay slot, which is pretty
common on RISC architectures, so this isn't a new problem.

The Intel Itanium Processor Reference Manual for Software Optimization says
that instructions are issued to a function unit regardless of the value of
the predicate.  However, it doesn't say in detail what happens after that,
but a reasonable assumption is that the processor goes ahead and executes
the operation, but doesn't store the result if the predicate evaluates to
false.

Jim