RE: Hyperthreading & 8.0

On Mon, 2002-09-23 at 15:05, Robert G. (Doc) Savage wrote:
> Is there any reason why dual Athlon MPs won't "hyperthread"? I could be
> wrong, but I thought late model Athlons have multiple instruction
> pipelines. Superscalar or something like that. How different is that
> from what Intel is promising?
> 
> --Doc Savage

I think even with superscalar architecture it still wastes many cycles
within the multiple execution pipelines during wait states (e.g. waiting
for the much slower system RAM or other off-chip devices).  I believe
hyperthreading has two sets of registers on chip rather than just one,
allowing for execution of another task during these otherwise wasted CPU
cycles.