[PATCH v3 1/3] scsi: ufs: spacemit: dt-bindings: Add UFS controller for K3 SoC
Yixun Lan <[email protected]> Thu, 06 Aug 2026 02:56:18 +0000
| Newsgroups | gmane.linux.ports.riscv,gmane.linux.scsi,gmane.linux.drivers.devicetree,gmane.linux.kernel |
|---|---|
| Message-ID | <[email protected]> |
Document the compatible for UFS (Universal Flash Storage) Host Controller which found in SpacemiT K3 SoC chip. Its features are listed below: - Compliant with MIPI UniPro v1.61 specification. - Compliant with M-PHY v3.0 specification. - Compliant with UFS HCI v2.1 specification. - Supports up to 2 Tx and 2 Rx lanes, up to HS-GEAR3 5.8 Gbps per lane. - Supports standard low-power hibernate to reduce power consumption. Signed-off-by: Yixun Lan <[email protected]> --- .../devicetree/bindings/ufs/spacemit,k3-ufshc.yaml | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml b/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml new file mode 100644 index 000000000000..dda533c852e8 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/spacemit,k3-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K3 SoC UFS Host Controller + +maintainers: + - Yixun Lan <[email protected]> + +properties: + compatible: + const: spacemit,k3-ufshc + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: aclk + - const: ref_clk + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +allOf: + - $ref: ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/spacemit,k3-clocks.h> + #include <dt-bindings/reset/spacemit,k3-resets.h> + #include <dt-bindings/interrupt-controller/irq.h> + ufs@c0e00000 { + compatible = "spacemit,k3-ufshc"; + reg = <0xc0e00000 0x40000>; + clocks = <&syscon_apmu CLK_APMU_UFS_ACLK>, + <&syscon_apmu CLK_APMU_UFS_REFCLK>; + clock-names = "aclk", "ref_clk"; + resets = <&syscon_apmu RESET_APMU_UFS_ACLK>; + interrupts = <135 IRQ_TYPE_LEVEL_HIGH>; + lanes-per-direction = <2>; + }; -- 2.55.0