[PATCH 05/11] m68knommu: remove a lot of unsed definitions for 532x ColdFire
<
[email protected] >
Fri, 21 Sep 2012 16:51:07 +1000
Newsgroups
gmane.linux.ports.m68k,gmane.linux.uclinux.devel
Message-ID
<[email protected] >
From: Greg Ungerer <[email protected] >
There are a lot of unused and uneccessary definitions in the header to
support the ColdFire 532x CPU family. Remove the junk.
Signed-off-by: Greg Ungerer <[email protected] >
---
arch/m68k/include/asm/m532xsim.h | 1033 +-------------------------------------
1 files changed, 1 insertions(+), 1032 deletions(-)
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 5ca7b29..3833370 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -152,42 +152,6 @@
#define MCFPM_PPMHR1 0xfc040038
#define MCFPM_LPCR 0xec090007
-/*********************************************************************
- *
- * Inter-IC (I2C) Module
- *
- *********************************************************************/
-
-/* Read/Write access macros for general use */
-#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
-#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
-#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
-#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
-#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
-
-#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
-
-#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
-#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
-#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
-#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
-#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
-#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
-
-#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
-#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
-#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
-#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
-#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
-#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
-#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
-
-#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
-
-
/*
* The M5329EVB board needs a help getting its devices initialized
* at kernel start time if dBUG doesn't set it up (for example
@@ -287,78 +251,6 @@
/*********************************************************************
*
- * DMA Timers (DTIM)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
-#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
-#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
-#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
-#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
-#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
-#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
-#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
-#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
-#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
-#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
-#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
-#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
-#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
-#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
-#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
-#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
-#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
-#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
-#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
-#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
-#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
-#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
-#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
-#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
-#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
-#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
-#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
-#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
-#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_DTIM_DTMR */
-#define MCF_DTIM_DTMR_RST (0x0001)
-#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
-#define MCF_DTIM_DTMR_FRR (0x0008)
-#define MCF_DTIM_DTMR_ORRI (0x0010)
-#define MCF_DTIM_DTMR_OM (0x0020)
-#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
-#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
-#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
-#define MCF_DTIM_DTMR_CE_FALL (0x0080)
-#define MCF_DTIM_DTMR_CE_RISE (0x0040)
-#define MCF_DTIM_DTMR_CE_NONE (0x0000)
-#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
-#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
-#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
-#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
-
-/* Bit definitions and macros for MCF_DTIM_DTXMR */
-#define MCF_DTIM_DTXMR_MODE16 (0x01)
-#define MCF_DTIM_DTXMR_DMAEN (0x80)
-
-/* Bit definitions and macros for MCF_DTIM_DTER */
-#define MCF_DTIM_DTER_CAP (0x01)
-#define MCF_DTIM_DTER_REF (0x02)
-
-/* Bit definitions and macros for MCF_DTIM_DTRR */
-#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCR */
-#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_DTIM_DTCN */
-#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
-
-/*********************************************************************
- *
* FlexBus Chip Selects (FBCS)
*
*********************************************************************/
@@ -1215,709 +1107,6 @@
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
-
-/*********************************************************************
- *
- * Interrupt Controller (INTC)
- *
- *********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
-#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
-#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
-#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
-#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
-#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
-#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
-#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
-#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
-#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
-#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
-#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
-#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
-#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
-#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
-#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
-#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
-#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
-#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
-#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
-#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
-#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
-#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
-#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
-#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
-#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
-#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
-#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
-#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
-#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
-#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
-#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
-#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
-#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
-#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
-#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
-#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
-#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
-#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
-#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
-#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
-#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
-#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
-#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
-#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
-#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
-#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
-#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
-#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
-#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
-#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
-#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
-#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
-#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
-#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
-#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
-#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
-#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
-#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
-#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
-#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
-#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
-#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
-#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
-#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
-#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
-#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
-#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
-#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
-#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
-#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
-#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
-#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
-#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
-#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
-#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
-#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
-#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
-#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
-#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
-#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
-#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
-#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
-#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
-#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
-#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
-#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
-#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
-#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
-#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
-#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
-#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
-#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
-#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
-#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
-#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
-#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
-#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
-#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
-#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
-#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
-#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
-#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
-#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
-#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
-#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
-#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
-#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
-#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
-#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
-#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
-#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
-#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
-#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
-#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
-#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
-#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
-#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
-#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
-#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
-#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
-#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
-#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
-#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
-#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
-#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
-#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
-#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
-#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
-#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
-#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
-#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
-#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
-#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
-#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
-#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
-#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
-#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
-#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
-#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
-#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
-#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
-#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
-#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
-#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
-#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
-#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
-#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
-#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
-#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
-#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
-#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
-#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
-#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
-#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
-#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
-#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
-#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
-#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
-#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
-#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
-#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
-#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
-#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
-#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
-#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
-#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
-#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
-#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
-#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
-#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
-#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
-#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
-#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
-#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
-#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
-#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
-#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
-#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
-#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
-#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
-#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
-#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
-#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
-#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
-#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
-#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
-#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
-#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
-#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
-#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
-#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
-#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
-#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
-#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
-#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
-#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
-#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
-#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
-#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
-#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
-#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
-#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
-#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
-#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
-#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
-#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
-#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
-#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
-#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
-#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
-#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
-#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
-#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
-#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
-#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
-#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
-#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
-#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
-#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
-#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
-#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
-#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
-#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
-#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
-#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
-#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
-#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
-#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
-#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
-#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
-#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
-#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
-#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
-#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
-#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
-#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
-#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
-#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
-#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
-#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
-#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
-#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
-#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
-#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
-#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
-#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
-#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
-#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
-#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
-#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
-#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
-#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_INTC_IPRH */
-#define MCF_INTC_IPRH_INT32 (0x00000001)
-#define MCF_INTC_IPRH_INT33 (0x00000002)
-#define MCF_INTC_IPRH_INT34 (0x00000004)
-#define MCF_INTC_IPRH_INT35 (0x00000008)
-#define MCF_INTC_IPRH_INT36 (0x00000010)
-#define MCF_INTC_IPRH_INT37 (0x00000020)
-#define MCF_INTC_IPRH_INT38 (0x00000040)
-#define MCF_INTC_IPRH_INT39 (0x00000080)
-#define MCF_INTC_IPRH_INT40 (0x00000100)
-#define MCF_INTC_IPRH_INT41 (0x00000200)
-#define MCF_INTC_IPRH_INT42 (0x00000400)
-#define MCF_INTC_IPRH_INT43 (0x00000800)
-#define MCF_INTC_IPRH_INT44 (0x00001000)
-#define MCF_INTC_IPRH_INT45 (0x00002000)
-#define MCF_INTC_IPRH_INT46 (0x00004000)
-#define MCF_INTC_IPRH_INT47 (0x00008000)
-#define MCF_INTC_IPRH_INT48 (0x00010000)
-#define MCF_INTC_IPRH_INT49 (0x00020000)
-#define MCF_INTC_IPRH_INT50 (0x00040000)
-#define MCF_INTC_IPRH_INT51 (0x00080000)
-#define MCF_INTC_IPRH_INT52 (0x00100000)
-#define MCF_INTC_IPRH_INT53 (0x00200000)
-#define MCF_INTC_IPRH_INT54 (0x00400000)
-#define MCF_INTC_IPRH_INT55 (0x00800000)
-#define MCF_INTC_IPRH_INT56 (0x01000000)
-#define MCF_INTC_IPRH_INT57 (0x02000000)
-#define MCF_INTC_IPRH_INT58 (0x04000000)
-#define MCF_INTC_IPRH_INT59 (0x08000000)
-#define MCF_INTC_IPRH_INT60 (0x10000000)
-#define MCF_INTC_IPRH_INT61 (0x20000000)
-#define MCF_INTC_IPRH_INT62 (0x40000000)
-#define MCF_INTC_IPRH_INT63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IPRL */
-#define MCF_INTC_IPRL_INT0 (0x00000001)
-#define MCF_INTC_IPRL_INT1 (0x00000002)
-#define MCF_INTC_IPRL_INT2 (0x00000004)
-#define MCF_INTC_IPRL_INT3 (0x00000008)
-#define MCF_INTC_IPRL_INT4 (0x00000010)
-#define MCF_INTC_IPRL_INT5 (0x00000020)
-#define MCF_INTC_IPRL_INT6 (0x00000040)
-#define MCF_INTC_IPRL_INT7 (0x00000080)
-#define MCF_INTC_IPRL_INT8 (0x00000100)
-#define MCF_INTC_IPRL_INT9 (0x00000200)
-#define MCF_INTC_IPRL_INT10 (0x00000400)
-#define MCF_INTC_IPRL_INT11 (0x00000800)
-#define MCF_INTC_IPRL_INT12 (0x00001000)
-#define MCF_INTC_IPRL_INT13 (0x00002000)
-#define MCF_INTC_IPRL_INT14 (0x00004000)
-#define MCF_INTC_IPRL_INT15 (0x00008000)
-#define MCF_INTC_IPRL_INT16 (0x00010000)
-#define MCF_INTC_IPRL_INT17 (0x00020000)
-#define MCF_INTC_IPRL_INT18 (0x00040000)
-#define MCF_INTC_IPRL_INT19 (0x00080000)
-#define MCF_INTC_IPRL_INT20 (0x00100000)
-#define MCF_INTC_IPRL_INT21 (0x00200000)
-#define MCF_INTC_IPRL_INT22 (0x00400000)
-#define MCF_INTC_IPRL_INT23 (0x00800000)
-#define MCF_INTC_IPRL_INT24 (0x01000000)
-#define MCF_INTC_IPRL_INT25 (0x02000000)
-#define MCF_INTC_IPRL_INT26 (0x04000000)
-#define MCF_INTC_IPRL_INT27 (0x08000000)
-#define MCF_INTC_IPRL_INT28 (0x10000000)
-#define MCF_INTC_IPRL_INT29 (0x20000000)
-#define MCF_INTC_IPRL_INT30 (0x40000000)
-#define MCF_INTC_IPRL_INT31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRH */
-#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
-#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
-#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
-#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
-#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
-#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
-#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
-#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
-#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
-#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
-#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
-#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
-#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
-#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
-#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
-#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
-#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
-#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
-#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
-#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
-#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
-#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
-#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
-#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
-#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
-#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
-#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
-#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
-#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
-#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
-#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
-#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_IMRL */
-#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
-#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
-#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
-#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
-#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
-#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
-#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
-#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
-#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
-#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
-#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
-#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
-#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
-#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
-#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
-#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
-#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
-#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
-#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
-#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
-#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
-#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
-#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
-#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
-#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
-#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
-#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
-#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
-#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
-#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
-#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
-#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCH */
-#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
-#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
-#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
-#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
-#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
-#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
-#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
-#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
-#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
-#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
-#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
-#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
-#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
-#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
-#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
-#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
-#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
-#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
-#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
-#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
-#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
-#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
-#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
-#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
-#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
-#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
-#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
-#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
-#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
-#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
-#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
-#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_INTFRCL */
-#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
-#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
-#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
-#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
-#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
-#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
-#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
-#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
-#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
-#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
-#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
-#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
-#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
-#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
-#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
-#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
-#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
-#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
-#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
-#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
-#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
-#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
-#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
-#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
-#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
-#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
-#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
-#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
-#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
-#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
-#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
-#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC_ICONFIG */
-#define MCF_INTC_ICONFIG_EMASK (0x0020)
-#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
-#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
-#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
-#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
-#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
-#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
-#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
-
-/* Bit definitions and macros for MCF_INTC_SIMR */
-#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CIMR */
-#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_CLMASK */
-#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SLMASK */
-#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_INTC_ICR */
-#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
-
-/* Bit definitions and macros for MCF_INTC_SWIACK */
-#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
-
-/* Bit definitions and macros for MCF_INTC_LIACK */
-#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
-
-/********************************************************************/
-/*********************************************************************
-*
-* LCD Controller (LCDC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
-#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
-#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
-#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
-#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
-#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
-#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
-#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
-#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
-#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
-#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
-#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
-#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
-#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
-#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
-#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
-#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
-#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
-#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
-#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
-#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
-#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
-#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
-#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
-#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
-#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
-
-/* Bit definitions and macros for MCF_LCDC_LSSAR */
-#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LSR */
-#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LVPWR */
-#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LCPR */
-#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
-#define MCF_LCDC_LCPR_OP (0x10000000)
-#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
-#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
-#define MCF_LCDC_LCPR_CC_OR (0x40000000)
-#define MCF_LCDC_LCPR_CC_XOR (0x80000000)
-#define MCF_LCDC_LCPR_CC_AND (0xC0000000)
-#define MCF_LCDC_LCPR_OP_ON (0x10000000)
-#define MCF_LCDC_LCPR_OP_OFF (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCWHBR */
-#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
-#define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
-#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
-
-/* Bit definitions and macros for MCF_LCDC_LCCMR */
-#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
-
-/* Bit definitions and macros for MCF_LCDC_LPCR */
-#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LPCR_SHARP (0x00000040)
-#define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
-#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
-#define MCF_LCDC_LPCR_ACDSEL (0x00008000)
-#define MCF_LCDC_LPCR_REV_VS (0x00010000)
-#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
-#define MCF_LCDC_LPCR_ENDSEL (0x00040000)
-#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
-#define MCF_LCDC_LPCR_OEPOL (0x00100000)
-#define MCF_LCDC_LPCR_CLKPOL (0x00200000)
-#define MCF_LCDC_LPCR_LPPOL (0x00400000)
-#define MCF_LCDC_LPCR_FLM (0x00800000)
-#define MCF_LCDC_LPCR_PIXPOL (0x01000000)
-#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
-#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
-#define MCF_LCDC_LPCR_COLOR (0x40000000)
-#define MCF_LCDC_LPCR_TFT (0x80000000)
-#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
-#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
-#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
-#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
-#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
-#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
-#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
-#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
-#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
-#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
-#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
-#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
-#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
-#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
-
-#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
-
-/* Bit definitions and macros for MCF_LCDC_LHCR */
-#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LVCR */
-#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
-#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for MCF_LCDC_LPOR */
-#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LPCCR */
-#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
-#define MCF_LCDC_LPCCR_CC_EN (0x00000100)
-#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
-#define MCF_LCDC_LPCCR_LDMSK (0x00008000)
-#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
-#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
-#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
-#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
-
-/* Bit definitions and macros for MCF_LCDC_LDCR */
-#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LDCR_BURST (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LRMCR */
-#define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
-
-/* Bit definitions and macros for MCF_LCDC_LICR */
-#define MCF_LCDC_LICR_INTCON (0x00000001)
-#define MCF_LCDC_LICR_INTSYN (0x00000004)
-#define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
-
-/* Bit definitions and macros for MCF_LCDC_LIER */
-#define MCF_LCDC_LIER_BOF_EN (0x00000001)
-#define MCF_LCDC_LIER_EOF_EN (0x00000002)
-#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
-#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
-#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
-#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
-#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
-#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LISR */
-#define MCF_LCDC_LISR_BOF (0x00000001)
-#define MCF_LCDC_LISR_EOF (0x00000002)
-#define MCF_LCDC_LISR_ERR_RES (0x00000004)
-#define MCF_LCDC_LISR_UDR_ERR (0x00000008)
-#define MCF_LCDC_LISR_GW_BOF (0x00000010)
-#define MCF_LCDC_LISR_GW_EOF (0x00000020)
-#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
-#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSAR */
-#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_LCDC_LGWSR */
-#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
-#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPOR */
-#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_LGWPR */
-#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
-#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
-
-/* Bit definitions and macros for MCF_LCDC_LGWCR */
-#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
-#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
-#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
-#define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
-#define MCF_LCDC_LGWCR_GWE (0x00400000)
-#define MCF_LCDC_LGWCR_GWCKE (0x00800000)
-#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_LCDC_LGWDCR */
-#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
-#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
-#define MCF_LCDC_LGWDCR_GWBT (0x80000000)
-
-/* Bit definitions and macros for MCF_LCDC_LSCR */
-#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
-#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
-#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
-#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
-#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
-#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
-#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
-
/*********************************************************************
*
* Phase Locked Loop (PLL)
@@ -2046,143 +1235,9 @@
#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
-/*********************************************************************
- *
- * FlexCAN module registers
- *
- *********************************************************************/
-#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
-#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
-#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
-#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
-#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
-#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
-#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
-#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
-#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
-#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
-#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
-
-#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
-#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
-#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
-
-/*
- * FlexCAN Module Configuration Register
- */
-#define CANMCR_MDIS (0x80000000)
-#define CANMCR_FRZ (0x40000000)
-#define CANMCR_HALT (0x10000000)
-#define CANMCR_SOFTRST (0x02000000)
-#define CANMCR_FRZACK (0x01000000)
-#define CANMCR_SUPV (0x00800000)
-#define CANMCR_MAXMB(x) ((x)&0x0F)
-
-/*
- * FlexCAN Control Register
- */
-#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
-#define CANCTRL_RJW(x) (((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK (0x00008000)
-#define CANCTRL_ERRMSK (0x00004000)
-#define CANCTRL_CLKSRC (0x00002000)
-#define CANCTRL_LPB (0x00001000)
-#define CANCTRL_SAMP (0x00000080)
-#define CANCTRL_BOFFREC (0x00000040)
-#define CANCTRL_TSYNC (0x00000020)
-#define CANCTRL_LBUF (0x00000010)
-#define CANCTRL_LOM (0x00000008)
-#define CANCTRL_PROPSEG(x) ((x)&0x07)
-
-/*
- * FlexCAN Error Counter Register
- */
-#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
-#define ERRCNT_TXECTR(x) ((x)&0xFF)
-
-/*
- * FlexCAN Error and Status Register
- */
-#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
-#define ERRSTAT_ACKERR (0x00002000)
-#define ERRSTAT_CRCERR (0x00001000)
-#define ERRSTAT_FRMERR (0x00000800)
-#define ERRSTAT_STFERR (0x00000400)
-#define ERRSTAT_TXWRN (0x00000200)
-#define ERRSTAT_RXWRN (0x00000100)
-#define ERRSTAT_IDLE (0x00000080)
-#define ERRSTAT_TXRX (0x00000040)
-#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
-#define ERRSTAT_BOFFINT (0x00000004)
-#define ERRSTAT_ERRINT (0x00000002)
-
/*
- * Interrupt Mask Register
- */
-#define IMASK_BUF15M (0x8000)
-#define IMASK_BUF14M (0x4000)
-#define IMASK_BUF13M (0x2000)
-#define IMASK_BUF12M (0x1000)
-#define IMASK_BUF11M (0x0800)
-#define IMASK_BUF10M (0x0400)
-#define IMASK_BUF9M (0x0200)
-#define IMASK_BUF8M (0x0100)
-#define IMASK_BUF7M (0x0080)
-#define IMASK_BUF6M (0x0040)
-#define IMASK_BUF5M (0x0020)
-#define IMASK_BUF4M (0x0010)
-#define IMASK_BUF3M (0x0008)
-#define IMASK_BUF2M (0x0004)
-#define IMASK_BUF1M (0x0002)
-#define IMASK_BUF0M (0x0001)
-#define IMASK_BUFnM(x) (0x1<<(x))
-#define IMASK_BUFF_ENABLE_ALL (0x1111)
-#define IMASK_BUFF_DISABLE_ALL (0x0000)
-
-/*
- * Interrupt Flag Register
- */
-#define IFLAG_BUF15M (0x8000)
-#define IFLAG_BUF14M (0x4000)
-#define IFLAG_BUF13M (0x2000)
-#define IFLAG_BUF12M (0x1000)
-#define IFLAG_BUF11M (0x0800)
-#define IFLAG_BUF10M (0x0400)
-#define IFLAG_BUF9M (0x0200)
-#define IFLAG_BUF8M (0x0100)
-#define IFLAG_BUF7M (0x0080)
-#define IFLAG_BUF6M (0x0040)
-#define IFLAG_BUF5M (0x0020)
-#define IFLAG_BUF4M (0x0010)
-#define IFLAG_BUF3M (0x0008)
-#define IFLAG_BUF2M (0x0004)
-#define IFLAG_BUF1M (0x0002)
-#define IFLAG_BUF0M (0x0001)
-#define IFLAG_BUFF_SET_ALL (0xFFFF)
-#define IFLAG_BUFF_CLEAR_ALL (0x0000)
-#define IFLAG_BUFnM(x) (0x1<<(x))
-
-/*
- * Message Buffers
- */
-#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
-#define MB_CNT_SRR (0x00400000)
-#define MB_CNT_IDE (0x00200000)
-#define MB_CNT_RTR (0x00100000)
-#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
-#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
-#define MB_ID_STD(x) (((x)&0x07FF)<<18)
-#define MB_ID_EXT(x) ((x)&0x3FFFF)
-
-/*********************************************************************
- *
* Edge Port Module (EPORT)
- *
- *********************************************************************/
-
-/* Register read/write macros */
+ */
#define MCFEPORT_EPPAR (0xFC094000)
#define MCFEPORT_EPDDR (0xFC094002)
#define MCFEPORT_EPIER (0xFC094003)
@@ -2190,91 +1245,5 @@
#define MCFEPORT_EPPDR (0xFC094005)
#define MCFEPORT_EPFR (0xFC094006)
-/* Bit definitions and macros for MCF_EPORT_EPPAR */
-#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
-#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
-#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
-#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
-#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
-#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
-#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
-#define MCF_EPORT_EPPAR_LEVEL (0)
-#define MCF_EPORT_EPPAR_RISING (1)
-#define MCF_EPORT_EPPAR_FALLING (2)
-#define MCF_EPORT_EPPAR_BOTH (3)
-#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
-#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
-#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
-#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
-#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
-#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
-#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
-#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
-#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
-#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
-#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
-#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
-#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
-#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
-#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
-#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
-#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
-#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
-#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
-#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
-#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
-#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
-#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
-#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
-#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
-#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
-#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
-#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
-
-/* Bit definitions and macros for MCF_EPORT_EPDDR */
-#define MCF_EPORT_EPDDR_EPDD1 (0x02)
-#define MCF_EPORT_EPDDR_EPDD2 (0x04)
-#define MCF_EPORT_EPDDR_EPDD3 (0x08)
-#define MCF_EPORT_EPDDR_EPDD4 (0x10)
-#define MCF_EPORT_EPDDR_EPDD5 (0x20)
-#define MCF_EPORT_EPDDR_EPDD6 (0x40)
-#define MCF_EPORT_EPDDR_EPDD7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPIER */
-#define MCF_EPORT_EPIER_EPIE1 (0x02)
-#define MCF_EPORT_EPIER_EPIE2 (0x04)
-#define MCF_EPORT_EPIER_EPIE3 (0x08)
-#define MCF_EPORT_EPIER_EPIE4 (0x10)
-#define MCF_EPORT_EPIER_EPIE5 (0x20)
-#define MCF_EPORT_EPIER_EPIE6 (0x40)
-#define MCF_EPORT_EPIER_EPIE7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPDR */
-#define MCF_EPORT_EPDR_EPD1 (0x02)
-#define MCF_EPORT_EPDR_EPD2 (0x04)
-#define MCF_EPORT_EPDR_EPD3 (0x08)
-#define MCF_EPORT_EPDR_EPD4 (0x10)
-#define MCF_EPORT_EPDR_EPD5 (0x20)
-#define MCF_EPORT_EPDR_EPD6 (0x40)
-#define MCF_EPORT_EPDR_EPD7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPPDR */
-#define MCF_EPORT_EPPDR_EPPD1 (0x02)
-#define MCF_EPORT_EPPDR_EPPD2 (0x04)
-#define MCF_EPORT_EPPDR_EPPD3 (0x08)
-#define MCF_EPORT_EPPDR_EPPD4 (0x10)
-#define MCF_EPORT_EPPDR_EPPD5 (0x20)
-#define MCF_EPORT_EPPDR_EPPD6 (0x40)
-#define MCF_EPORT_EPPDR_EPPD7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPFR */
-#define MCF_EPORT_EPFR_EPF1 (0x02)
-#define MCF_EPORT_EPFR_EPF2 (0x04)
-#define MCF_EPORT_EPFR_EPF3 (0x08)
-#define MCF_EPORT_EPFR_EPF4 (0x10)
-#define MCF_EPORT_EPFR_EPF5 (0x20)
-#define MCF_EPORT_EPFR_EPF6 (0x40)
-#define MCF_EPORT_EPFR_EPF7 (0x80)
-
/********************************************************************/
#endif /* m532xsim_h */
--
1.7.0.4